package sifive.blocks.devices.uart
import Chisel._
-import config.Field
-import diplomacy.LazyModule
-import rocketchip.{
- HasTopLevelNetworks,
- HasTopLevelNetworksBundle,
- HasTopLevelNetworksModule
-}
-import uncore.tilelink2._
-
+import freechips.rocketchip.config.Field
+import freechips.rocketchip.coreplex.{HasPeripheryBus, PeripheryBusParams, HasInterruptBus}
+import freechips.rocketchip.diplomacy.{LazyModule, LazyMultiIOModuleImp}
import sifive.blocks.devices.gpio.{GPIOPin, GPIOOutputPinCtrl, GPIOInputPinCtrl}
import sifive.blocks.util.ShiftRegisterInit
case object PeripheryUARTKey extends Field[Seq[UARTParams]]
-trait HasPeripheryUART extends HasTopLevelNetworks {
- val uartParams = p(PeripheryUARTKey)
+trait HasPeripheryUART extends HasPeripheryBus with HasInterruptBus {
+ val uartParams = p(PeripheryUARTKey)
+ val divinit = (p(PeripheryBusParams).frequency / 115200).toInt
val uarts = uartParams map { params =>
- val uart = LazyModule(new TLUART(peripheryBusBytes, params))
- uart.node := TLFragmenter(peripheryBusBytes, cacheBlockBytes)(peripheryBus.node)
- intBus.intnode := uart.intnode
+ val uart = LazyModule(new TLUART(pbus.beatBytes, params.copy(divisorInit = divinit)))
+ uart.node := pbus.toVariableWidthSlaves
+ ibus.fromSync := uart.intnode
uart
}
}
-trait HasPeripheryUARTBundle extends HasTopLevelNetworksBundle {
- val outer: HasPeripheryUART
- val uarts = Vec(outer.uartParams.size, new UARTPortIO)
+trait HasPeripheryUARTBundle {
+ val uarts: Vec[UARTPortIO]
+
+ def tieoffUARTs(dummy: Int = 1) {
+ uarts.foreach { _.rxd := UInt(1) }
+ }
+
+ def UARTtoGPIOPins(syncStages: Int = 0): Seq[UARTPinsIO] = uarts.map { u =>
+ val pins = Module(new UARTGPIOPort(syncStages))
+ pins.io.uart <> u
+ pins.io.pins
+ }
}
-trait HasPeripheryUARTModule extends HasTopLevelNetworksModule {
+trait HasPeripheryUARTModuleImp extends LazyMultiIOModuleImp with HasPeripheryUARTBundle {
val outer: HasPeripheryUART
- val io: HasPeripheryUARTBundle
- (io.uarts zip outer.uarts).foreach { case (io, device) =>
+ val uarts = IO(Vec(outer.uartParams.size, new UARTPortIO))
+
+ (uarts zip outer.uarts).foreach { case (io, device) =>
io <> device.module.io.port
}
}