uart: use PeripheryBusParams.frequency to calculate default divisor (#28)

[sifive-blocks.git] / src / main / scala / devices / uart / UARTPeriphery.scala

diff --git a/src/main/scala/devices/uart/UARTPeriphery.scala b/src/main/scala/devices/uart/UARTPeriphery.scala
index fd5bc35db4838105187197ef82622c31c948a2d1..677394f2581ca436bbf565af0d4f568cff208c23 100644 (file)
--- a/src/main/scala/devices/uart/UARTPeriphery.scala
+++ b/src/main/scala/devices/uart/UARTPeriphery.scala
@@ -2,37 +2,44 @@
 package sifive.blocks.devices.uart
 
 import Chisel._
-import config._
-import diplomacy._
-import uncore.tilelink2._
-import rocketchip._
-
+import freechips.rocketchip.config.Field
+import freechips.rocketchip.coreplex.{HasPeripheryBus, PeripheryBusParams, HasInterruptBus}
+import freechips.rocketchip.diplomacy.{LazyModule, LazyMultiIOModuleImp}
 import sifive.blocks.devices.gpio.{GPIOPin, GPIOOutputPinCtrl, GPIOInputPinCtrl}
 import sifive.blocks.util.ShiftRegisterInit
 
-trait PeripheryUART {
-  this: TopNetwork {
-    val uartConfigs: Seq[UARTConfig]
-  } =>
-  val uartDevices = uartConfigs.zipWithIndex.map { case (c, i) =>
-    val uart = LazyModule(new UART(c) { override lazy val valName = Some(s"uart$i") } )
-    uart.node := TLFragmenter(peripheryBusConfig.beatBytes, cacheBlockBytes)(peripheryBus.node)
-    intBus.intnode := uart.intnode
+case object PeripheryUARTKey extends Field[Seq[UARTParams]]
+
+trait HasPeripheryUART extends HasPeripheryBus with HasInterruptBus {
+  val uartParams = p(PeripheryUARTKey)
+  val divinit = (p(PeripheryBusParams).frequency / 115200).toInt
+  val uarts = uartParams map { params =>
+    val uart = LazyModule(new TLUART(pbus.beatBytes, params.copy(divisorInit = divinit)))
+    uart.node := pbus.toVariableWidthSlaves
+    ibus.fromSync := uart.intnode
     uart
   }
 }
 
-trait PeripheryUARTBundle {
-  this: { val uartConfigs: Seq[UARTConfig] } =>
-  val uarts = Vec(uartConfigs.size, new UARTPortIO)
+trait HasPeripheryUARTBundle {
+  val uarts: Vec[UARTPortIO]
+
+  def tieoffUARTs(dummy: Int = 1) {
+    uarts.foreach { _.rxd := UInt(1) }
+  }
+
+  def UARTtoGPIOPins(syncStages: Int = 0): Seq[UARTPinsIO] = uarts.map { u =>
+    val pins = Module(new UARTGPIOPort(syncStages))
+    pins.io.uart <> u
+    pins.io.pins
+  }
 }
 
-trait PeripheryUARTModule {
-  this: TopNetworkModule {
-    val outer: PeripheryUART
-    val io: PeripheryUARTBundle
-  } =>
-  (io.uarts zip outer.uartDevices).foreach { case (io, device) =>
+trait HasPeripheryUARTModuleImp extends LazyMultiIOModuleImp with HasPeripheryUARTBundle {
+  val outer: HasPeripheryUART
+  val uarts = IO(Vec(outer.uartParams.size, new UARTPortIO))
+
+  (uarts zip outer.uarts).foreach { case (io, device) =>
     io <> device.module.io.port
   }
 }