Refactor package hierarchy.

[sifive-blocks.git] / src / main / scala / devices / uart / UARTPeriphery.scala

diff --git a/src/main/scala/devices/uart/UARTPeriphery.scala b/src/main/scala/devices/uart/UARTPeriphery.scala
index 58b1c9e779fe3564228f6f95169138a9ec63b0c2..b070a42a27b9e3c954f555aae884a66c2f22845e 100644 (file)
--- a/src/main/scala/devices/uart/UARTPeriphery.scala
+++ b/src/main/scala/devices/uart/UARTPeriphery.scala
@@ -2,11 +2,10 @@
 package sifive.blocks.devices.uart
 
 import Chisel._
-import config.Field
-import diplomacy.{LazyModule, LazyMultiIOModuleImp}
-import rocketchip.HasSystemNetworks
-import uncore.tilelink2.TLFragmenter
-
+import freechips.rocketchip.config.Field
+import freechips.rocketchip.diplomacy.{LazyModule, LazyMultiIOModuleImp}
+import freechips.rocketchip.chip.HasSystemNetworks
+import freechips.rocketchip.tilelink.TLFragmenter
 import sifive.blocks.devices.gpio.{GPIOPin, GPIOOutputPinCtrl, GPIOInputPinCtrl}
 import sifive.blocks.util.ShiftRegisterInit
 
@@ -30,9 +29,9 @@ trait HasPeripheryUARTBundle {
   }
 
   def UARTtoGPIOPins(syncStages: Int = 0): Seq[UARTPinsIO] = uarts.map { u =>
-    val pin = Module(new UARTGPIOPort(syncStages))
-    pin.io.uart <> u
-    pin.io.pins
+    val pins = Module(new UARTGPIOPort(syncStages))
+    pins.io.uart <> u
+    pins.io.pins
   }
 }