Use AXI4 mem key

[sifive-blocks.git] / src / main / scala / devices / xilinxvc707mig / XilinxVC707MIG.scala

diff --git a/src/main/scala/devices/xilinxvc707mig/XilinxVC707MIG.scala b/src/main/scala/devices/xilinxvc707mig/XilinxVC707MIG.scala
index 58d14f4de44c3a28234abf15d54ebb222a04a7d5..07f5562688adbe27501a12ed61adbb34c6ce7ee9 100644 (file)
--- a/src/main/scala/devices/xilinxvc707mig/XilinxVC707MIG.scala
+++ b/src/main/scala/devices/xilinxvc707mig/XilinxVC707MIG.scala
@@ -3,27 +3,28 @@ package sifive.blocks.devices.xilinxvc707mig
 
 import Chisel._
 import chisel3.experimental.{Analog,attach}
-import config._
-import diplomacy._
-import uncore.tilelink2._
-import uncore.axi4._
-import rocketchip._
+import freechips.rocketchip.amba.axi4._
+import freechips.rocketchip.config.Parameters
+import freechips.rocketchip.coreplex._
+import freechips.rocketchip.diplomacy._
+import freechips.rocketchip.tilelink._
 import sifive.blocks.ip.xilinx.vc707mig.{VC707MIGIOClocksReset, VC707MIGIODDR, vc707mig}
 
-trait HasXilinxVC707MIGParameters {
-}
+case class XilinxVC707MIGParams(
+  depthGB : Int
+)
 
-class XilinxVC707MIGPads extends Bundle with VC707MIGIODDR
+class XilinxVC707MIGPads(depthGB : Integer) extends VC707MIGIODDR(depthGB)
 
-class XilinxVC707MIGIO extends Bundle with VC707MIGIODDR
-                                      with VC707MIGIOClocksReset
+class XilinxVC707MIGIO(depthGB : Integer) extends VC707MIGIODDR(depthGB) with VC707MIGIOClocksReset
 
-class XilinxVC707MIG(implicit p: Parameters) extends LazyModule with HasXilinxVC707MIGParameters {
+class XilinxVC707MIG(c : XilinxVC707MIGParams)(implicit p: Parameters) extends LazyModule {
+  require((c.depthGB==1) || (c.depthGB==4),"XilinxVC707MIG supports 1GB and 4GB depth configuraton only")
   val device = new MemoryDevice
   val node = TLInputNode()
   val axi4 = AXI4InternalOutputNode(Seq(AXI4SlavePortParameters(
     slaves = Seq(AXI4SlaveParameters(
-      address = Seq(AddressSet(p(ExtMem).base, p(ExtMem).size-1)),
+      address = p(AXI4MemPortKey).address,
       resources     = device.reg,
       regionType    = RegionType.UNCACHED,
       executable    = true,
@@ -32,9 +33,9 @@ class XilinxVC707MIG(implicit p: Parameters) extends LazyModule with HasXilinxVC
     beatBytes = 8)))
 
   val xing    = LazyModule(new TLAsyncCrossing)
-  val toaxi4  = LazyModule(new TLToAXI4(beatBytes = 8))
+  val toaxi4  = LazyModule(new TLToAXI4(beatBytes = 8, adapterName = Some("mem"), stripBits = 1))
   val indexer = LazyModule(new AXI4IdIndexer(idBits = 4))
-  val deint   = LazyModule(new AXI4Deinterleaver(p(coreplex.CacheBlockBytes)))
+  val deint   = LazyModule(new AXI4Deinterleaver(p(CacheBlockBytes)))
   val yank    = LazyModule(new AXI4UserYanker)
   val buffer  = LazyModule(new AXI4Buffer)
 
@@ -48,12 +49,12 @@ class XilinxVC707MIG(implicit p: Parameters) extends LazyModule with HasXilinxVC
 
   lazy val module = new LazyModuleImp(this) {
     val io = new Bundle {
-      val port = new XilinxVC707MIGIO
+      val port = new XilinxVC707MIGIO(c.depthGB)
       val tl = node.bundleIn
     }
 
     //MIG black box instantiation
-    val blackbox = Module(new vc707mig)
+    val blackbox = Module(new vc707mig(c.depthGB))
 
     //pins to top level
 
@@ -77,9 +78,8 @@ class XilinxVC707MIG(implicit p: Parameters) extends LazyModule with HasXilinxVC
     io.port.ddr3_odt          := blackbox.io.ddr3_odt
 
     //inputs
-    //differential system clock
-    blackbox.io.sys_clk_n     := io.port.sys_clk_n
-    blackbox.io.sys_clk_p     := io.port.sys_clk_p
+    //NO_BUFFER clock
+    blackbox.io.sys_clk_i     := io.port.sys_clk_i
 
     //user interface signals
     val axi_async = axi4.bundleIn(0)