import Chisel._
import chisel3.experimental.{Analog,attach}
-import config._
-import diplomacy._
-import uncore.tilelink2._
-import uncore.axi4._
-import rocketchip._
+import freechips.rocketchip.amba.axi4._
+import freechips.rocketchip.config.Parameters
+import freechips.rocketchip.coreplex._
+import freechips.rocketchip.diplomacy._
+import freechips.rocketchip.tilelink._
import sifive.blocks.ip.xilinx.vc707mig.{VC707MIGIOClocksReset, VC707MIGIODDR, vc707mig}
-trait HasXilinxVC707MIGParameters {
-}
+case class XilinxVC707MIGParams(
+ depthGB : Int
+)
-class XilinxVC707MIGPads extends Bundle with VC707MIGIODDR
+class XilinxVC707MIGPads(depthGB : Integer) extends VC707MIGIODDR(depthGB)
-class XilinxVC707MIGIO extends Bundle with VC707MIGIODDR
- with VC707MIGIOClocksReset
+class XilinxVC707MIGIO(depthGB : Integer) extends VC707MIGIODDR(depthGB) with VC707MIGIOClocksReset
-class XilinxVC707MIG(implicit p: Parameters) extends LazyModule with HasXilinxVC707MIGParameters {
+class XilinxVC707MIG(c : XilinxVC707MIGParams)(implicit p: Parameters) extends LazyModule {
+ require((c.depthGB==1) || (c.depthGB==4),"XilinxVC707MIG supports 1GB and 4GB depth configuraton only")
val device = new MemoryDevice
val node = TLInputNode()
val axi4 = AXI4InternalOutputNode(Seq(AXI4SlavePortParameters(
slaves = Seq(AXI4SlaveParameters(
- address = Seq(AddressSet(p(ExtMem).base, p(ExtMem).size-1)),
+ address = p(AXI4MemPortKey).address,
resources = device.reg,
regionType = RegionType.UNCACHED,
executable = true,
beatBytes = 8)))
val xing = LazyModule(new TLAsyncCrossing)
- val toaxi4 = LazyModule(new TLToAXI4(beatBytes = 8))
+ val toaxi4 = LazyModule(new TLToAXI4(beatBytes = 8, adapterName = Some("mem"), stripBits = 1))
val indexer = LazyModule(new AXI4IdIndexer(idBits = 4))
- val deint = LazyModule(new AXI4Deinterleaver(p(coreplex.CacheBlockBytes)))
+ val deint = LazyModule(new AXI4Deinterleaver(p(CacheBlockBytes)))
val yank = LazyModule(new AXI4UserYanker)
+ val buffer = LazyModule(new AXI4Buffer)
xing.node := node
val monitor = (toaxi4.node := xing.node)
- axi4 := yank.node
+ axi4 := buffer.node
+ buffer.node := yank.node
yank.node := deint.node
deint.node := indexer.node
indexer.node := toaxi4.node
lazy val module = new LazyModuleImp(this) {
val io = new Bundle {
- val port = new XilinxVC707MIGIO
+ val port = new XilinxVC707MIGIO(c.depthGB)
val tl = node.bundleIn
}
//MIG black box instantiation
- val blackbox = Module(new vc707mig)
+ val blackbox = Module(new vc707mig(c.depthGB))
//pins to top level
io.port.ddr3_odt := blackbox.io.ddr3_odt
//inputs
- //differential system clock
- blackbox.io.sys_clk_n := io.port.sys_clk_n
- blackbox.io.sys_clk_p := io.port.sys_clk_p
+ //NO_BUFFER clock
+ blackbox.io.sys_clk_i := io.port.sys_clk_i
//user interface signals
val axi_async = axi4.bundleIn(0)
xing.module.io.in_reset := reset
xing.module.io.out_clock := blackbox.io.ui_clk
xing.module.io.out_reset := blackbox.io.ui_clk_sync_rst
- (Seq(toaxi4, indexer, deint, yank) ++ monitor) foreach { lm =>
+ (Seq(toaxi4, indexer, deint, yank, buffer) ++ monitor) foreach { lm =>
lm.module.clock := blackbox.io.ui_clk
lm.module.reset := blackbox.io.ui_clk_sync_rst
}