u500vc707devkit 4GB : new address map allows switch to paramterization with address...

[sifive-blocks.git] / src / main / scala / devices / xilinxvc707mig / XilinxVC707MIG.scala

diff --git a/src/main/scala/devices/xilinxvc707mig/XilinxVC707MIG.scala b/src/main/scala/devices/xilinxvc707mig/XilinxVC707MIG.scala
index 07f5562688adbe27501a12ed61adbb34c6ce7ee9..5351cf0c2d2eef0a597a552d295c9a0d9deeecf6 100644 (file)
--- a/src/main/scala/devices/xilinxvc707mig/XilinxVC707MIG.scala
+++ b/src/main/scala/devices/xilinxvc707mig/XilinxVC707MIG.scala
@@ -11,20 +11,29 @@ import freechips.rocketchip.tilelink._
 import sifive.blocks.ip.xilinx.vc707mig.{VC707MIGIOClocksReset, VC707MIGIODDR, vc707mig}
 
 case class XilinxVC707MIGParams(
-  depthGB : Int
+  address : Seq[AddressSet]
 )
 
-class XilinxVC707MIGPads(depthGB : Integer) extends VC707MIGIODDR(depthGB)
+class XilinxVC707MIGPads(depth : BigInt) extends VC707MIGIODDR(depth) {
+  def this(c : XilinxVC707MIGParams) {
+    this(AddressRange.fromSets(c.address).head.size)
+  }
+}
 
-class XilinxVC707MIGIO(depthGB : Integer) extends VC707MIGIODDR(depthGB) with VC707MIGIOClocksReset
+class XilinxVC707MIGIO(depth : BigInt) extends VC707MIGIODDR(depth) with VC707MIGIOClocksReset
 
 class XilinxVC707MIG(c : XilinxVC707MIGParams)(implicit p: Parameters) extends LazyModule {
-  require((c.depthGB==1) || (c.depthGB==4),"XilinxVC707MIG supports 1GB and 4GB depth configuraton only")
+  val ranges = AddressRange.fromSets(c.address)
+  require (ranges.size == 1, "DDR range must be contiguous")
+  val offset = ranges.head.base
+  val depth = ranges.head.size
+  require((depth==0x40000000L) || (depth==0x100000000L)) //1GB or 4GB depth
+  
   val device = new MemoryDevice
   val node = TLInputNode()
   val axi4 = AXI4InternalOutputNode(Seq(AXI4SlavePortParameters(
-    slaves = Seq(AXI4SlaveParameters(
-      address = p(AXI4MemPortKey).address,
+      slaves = Seq(AXI4SlaveParameters(
+      address       = c.address,
       resources     = device.reg,
       regionType    = RegionType.UNCACHED,
       executable    = true,
@@ -49,12 +58,12 @@ class XilinxVC707MIG(c : XilinxVC707MIGParams)(implicit p: Parameters) extends L
 
   lazy val module = new LazyModuleImp(this) {
     val io = new Bundle {
-      val port = new XilinxVC707MIGIO(c.depthGB)
+      val port = new XilinxVC707MIGIO(depth)
       val tl = node.bundleIn
     }
 
     //MIG black box instantiation
-    val blackbox = Module(new vc707mig(c.depthGB))
+    val blackbox = Module(new vc707mig(depth))
 
     //pins to top level
 
@@ -103,9 +112,12 @@ class XilinxVC707MIG(c : XilinxVC707MIGParams)(implicit p: Parameters) extends L
     //app_ref_ack             := unconnected
     //app_zq_ack              := unconnected
 
+    val awaddr = axi_async.aw.bits.addr - UInt(offset)
+    val araddr = axi_async.ar.bits.addr - UInt(offset)
+
     //slave AXI interface write address ports
     blackbox.io.s_axi_awid    := axi_async.aw.bits.id
-    blackbox.io.s_axi_awaddr  := axi_async.aw.bits.addr //truncation ??
+    blackbox.io.s_axi_awaddr  := awaddr //truncated
     blackbox.io.s_axi_awlen   := axi_async.aw.bits.len
     blackbox.io.s_axi_awsize  := axi_async.aw.bits.size
     blackbox.io.s_axi_awburst := axi_async.aw.bits.burst
@@ -131,7 +143,7 @@ class XilinxVC707MIG(c : XilinxVC707MIGParams)(implicit p: Parameters) extends L
 
     //slave AXI interface read address ports
     blackbox.io.s_axi_arid    := axi_async.ar.bits.id
-    blackbox.io.s_axi_araddr  := axi_async.ar.bits.addr //truncation ??
+    blackbox.io.s_axi_araddr  := araddr // truncated
     blackbox.io.s_axi_arlen   := axi_async.ar.bits.len
     blackbox.io.s_axi_arsize  := axi_async.ar.bits.size
     blackbox.io.s_axi_arburst := axi_async.ar.bits.burst