package sifive.blocks.devices.xilinxvc707mig
import Chisel._
+import freechips.rocketchip.config._
import freechips.rocketchip.coreplex.HasMemoryBus
-import freechips.rocketchip.diplomacy.{LazyModule, LazyMultiIOModuleImp}
+import freechips.rocketchip.diplomacy.{LazyModule, LazyMultiIOModuleImp, AddressRange}
+
+case object MemoryXilinxDDRKey extends Field[XilinxVC707MIGParams]
trait HasMemoryXilinxVC707MIG extends HasMemoryBus {
val module: HasMemoryXilinxVC707MIGModuleImp
- val xilinxvc707mig = LazyModule(new XilinxVC707MIG)
+ val xilinxvc707mig = LazyModule(new XilinxVC707MIG(p(MemoryXilinxDDRKey)))
require(nMemoryChannels == 1, "Coreplex must have 1 master memory port")
xilinxvc707mig.node := memBuses.head.toDRAMController
trait HasMemoryXilinxVC707MIGModuleImp extends LazyMultiIOModuleImp
with HasMemoryXilinxVC707MIGBundle {
val outer: HasMemoryXilinxVC707MIG
- val xilinxvc707mig = IO(new XilinxVC707MIGIO)
+ val ranges = AddressRange.fromSets(p(MemoryXilinxDDRKey).address)
+ require (ranges.size == 1, "DDR range must be contiguous")
+ val depth = ranges.head.size
+ val xilinxvc707mig = IO(new XilinxVC707MIGIO(depth))
xilinxvc707mig <> outer.xilinxvc707mig.module.io.port
}