package sifive.blocks.devices.xilinxvc707mig
import Chisel._
-import diplomacy._
-import rocketchip.{
- HasTopLevelNetworks,
- HasTopLevelNetworksModule,
- HasTopLevelNetworksBundle
-}
-import coreplex.BankedL2Config
+import freechips.rocketchip.config._
+import freechips.rocketchip.coreplex.HasMemoryBus
+import freechips.rocketchip.diplomacy.{LazyModule, LazyMultiIOModuleImp, AddressRange}
+
+case object MemoryXilinxDDRKey extends Field[XilinxVC707MIGParams]
+
+trait HasMemoryXilinxVC707MIG extends HasMemoryBus {
+ val module: HasMemoryXilinxVC707MIGModuleImp
-trait HasPeripheryXilinxVC707MIG extends HasTopLevelNetworks {
- val module: HasPeripheryXilinxVC707MIGModule
+ val xilinxvc707mig = LazyModule(new XilinxVC707MIG(p(MemoryXilinxDDRKey)))
- val xilinxvc707mig = LazyModule(new XilinxVC707MIG)
- require(p(BankedL2Config).nMemoryChannels == 1, "Coreplex must have 1 master memory port")
- xilinxvc707mig.node := mem(0).node
+ require(nMemoryChannels == 1, "Coreplex must have 1 master memory port")
+ xilinxvc707mig.node := memBuses.head.toDRAMController
}
-trait HasPeripheryXilinxVC707MIGBundle extends HasTopLevelNetworksBundle {
- val xilinxvc707mig = new XilinxVC707MIGIO
+trait HasMemoryXilinxVC707MIGBundle {
+ val xilinxvc707mig: XilinxVC707MIGIO
+ def connectXilinxVC707MIGToPads(pads: XilinxVC707MIGPads) {
+ pads <> xilinxvc707mig
+ }
}
-trait HasPeripheryXilinxVC707MIGModule extends HasTopLevelNetworksModule {
- val outer: HasPeripheryXilinxVC707MIG
- val io: HasPeripheryXilinxVC707MIGBundle
+trait HasMemoryXilinxVC707MIGModuleImp extends LazyMultiIOModuleImp
+ with HasMemoryXilinxVC707MIGBundle {
+ val outer: HasMemoryXilinxVC707MIG
+ val ranges = AddressRange.fromSets(p(MemoryXilinxDDRKey).address)
+ require (ranges.size == 1, "DDR range must be contiguous")
+ val depth = ranges.head.size
+ val xilinxvc707mig = IO(new XilinxVC707MIGIO(depth))
- io.xilinxvc707mig <> outer.xilinxvc707mig.module.io.port
+ xilinxvc707mig <> outer.xilinxvc707mig.module.io.port
}