HasTopLevelNetworksModule,
HasTopLevelNetworksBundle
}
-import uncore.tilelink2.TLWidthWidget
+import uncore.tilelink2._
trait HasPeripheryXilinxVC707PCIeX1 extends HasTopLevelNetworks {
val xilinxvc707pcie = LazyModule(new XilinxVC707PCIeX1)
- l2FrontendBus.node := xilinxvc707pcie.master
- xilinxvc707pcie.slave := TLWidthWidget(socBusConfig.beatBytes)(socBus.node)
- xilinxvc707pcie.control := TLWidthWidget(socBusConfig.beatBytes)(socBus.node)
- intBus.intnode := xilinxvc707pcie.intnode
+ private val intXing = LazyModule(new IntXing)
+
+ fsb.node := TLAsyncCrossingSink()(xilinxvc707pcie.master)
+ xilinxvc707pcie.slave := TLAsyncCrossingSource()(TLWidthWidget(socBusConfig.beatBytes)(socBus.node))
+ xilinxvc707pcie.control := TLAsyncCrossingSource()(TLWidthWidget(socBusConfig.beatBytes)(socBus.node))
+ intBus.intnode := intXing.intnode
+ intXing.intnode := xilinxvc707pcie.intnode
}
trait HasPeripheryXilinxVC707PCIeX1Bundle extends HasTopLevelNetworksBundle {
val io: HasPeripheryXilinxVC707PCIeX1Bundle
io.xilinxvc707pcie <> outer.xilinxvc707pcie.module.io.port
+
+ outer.xilinxvc707pcie.module.clock := outer.xilinxvc707pcie.module.io.port.axi_aclk_out
+ outer.xilinxvc707pcie.module.reset := ~io.xilinxvc707pcie.axi_aresetn
}