vc707axi: track rocketchip API changes (#16)

[sifive-blocks.git] / src / main / scala / ip / xilinx / vc707axi_to_pcie_x1 / vc707axi_to_pcie_x1.scala

diff --git a/src/main/scala/ip/xilinx/vc707axi_to_pcie_x1/vc707axi_to_pcie_x1.scala b/src/main/scala/ip/xilinx/vc707axi_to_pcie_x1/vc707axi_to_pcie_x1.scala
index d9ffe8b9e7cd42f5d159095410ee92fd673b9047..ac9745f46672dc61b9a970021fa7ab4e6d77b8bc 100644 (file)
--- a/src/main/scala/ip/xilinx/vc707axi_to_pcie_x1/vc707axi_to_pcie_x1.scala
+++ b/src/main/scala/ip/xilinx/vc707axi_to_pcie_x1/vc707axi_to_pcie_x1.scala
@@ -181,7 +181,7 @@ class VC707AXIToPCIeX1(implicit p:Parameters) extends LazyModule
         "device_type"        -> Seq(ResourceString("pci")),
         "interrupt-map-mask" -> Seq(0, 0, 0, 7).flatMap(ofInt),
         "interrupt-map"      -> Seq(1, 2, 3, 4).flatMap(ofMap),
-        "ranges"             -> resources("ranges").map { case Binding(_, ResourceAddress(address, _, _, _)) =>
+        "ranges"             -> resources("ranges").map { case Binding(_, ResourceAddress(address, _, _, _, _)) =>
                                                                ResourceMapping(address, BigInt(0x02000000) << 64) },
         "interrupt-controller" -> Seq(ResourceMap(labels = Seq(intc), value = Map(
           "interrupt-controller" -> Nil,
@@ -205,11 +205,13 @@ class VC707AXIToPCIeX1(implicit p:Parameters) extends LazyModule
       address       = List(AddressSet(0x50000000L, 0x03ffffffL)),
       resources     = device.reg,
       supportsWrite = TransferSizes(1, 4),
-      supportsRead  = TransferSizes(1, 4))),
+      supportsRead  = TransferSizes(1, 4),
+      interleavedId = Some(0))), // AXI4-Lite never interleaves responses
     beatBytes = 4)))
 
   val master = AXI4MasterNode(Seq(AXI4MasterPortParameters(
     masters = Seq(AXI4MasterParameters(
+      name    = "VC707 PCIe",
       id      = IdRange(0, 1),
       aligned = false)))))