u500vc707devkit 4GB : new address map allows switch to paramterization with address...

[sifive-blocks.git] / src / main / scala / ip / xilinx / vc707mig / vc707mig.scala

diff --git a/src/main/scala/ip/xilinx/vc707mig/vc707mig.scala b/src/main/scala/ip/xilinx/vc707mig/vc707mig.scala
index d7b522fd7eaa0ab38c7a67638387353fe60ddeb5..7b9ace36b64f1e170dfd86cb0c30ac5125c8a078 100644 (file)
--- a/src/main/scala/ip/xilinx/vc707mig/vc707mig.scala
+++ b/src/main/scala/ip/xilinx/vc707mig/vc707mig.scala
@@ -3,14 +3,15 @@ package sifive.blocks.ip.xilinx.vc707mig
 
 import Chisel._
 import chisel3.experimental.{Analog,attach}
-import config._
-import junctions._
+import freechips.rocketchip.util.GenericParameterizedBundle
+import freechips.rocketchip.config._
 
 // IP VLNV: xilinx.com:customize_ip:vc707mig:1.0
 // Black Box
 
-trait VC707MIGIODDR extends Bundle {
-  val ddr3_addr             = Bits(OUTPUT,14)
+class VC707MIGIODDR(depth : BigInt) extends GenericParameterizedBundle(depth) {
+  require((depth==0x40000000L) || (depth==0x100000000L),"VC707MIGIODDR supports 1GB and 4GB depth configuraton only")
+  val ddr3_addr             = Bits(OUTPUT,if(depth==0x40000000L) 14 else 16)
   val ddr3_ba               = Bits(OUTPUT,3)
   val ddr3_ras_n            = Bool(OUTPUT)
   val ddr3_cas_n            = Bool(OUTPUT)
@@ -45,10 +46,15 @@ trait VC707MIGIOClocksReset extends Bundle {
 
 //scalastyle:off
 //turn off linter: blackbox name must match verilog module 
-class vc707mig(implicit val p:Parameters) extends BlackBox
+class vc707mig(depth : BigInt)(implicit val p:Parameters) extends BlackBox
 {
-  val io = new Bundle with VC707MIGIODDR
-                      with VC707MIGIOClocksReset {
+  private val oneGB  : BigInt = 0x40000000L
+  private val fourGB : BigInt = 0x100000000L
+  require((depth==oneGB) || (depth==fourGB),"vc707mig supports 1GB and 4GB depth configuraton only")
+
+  override def desiredName = if(depth==fourGB) "vc707mig4gb" else "vc707mig"
+
+  val io = new VC707MIGIODDR(depth) with VC707MIGIOClocksReset {
     // User interface signals
     val app_sr_req            = Bool(INPUT)
     val app_ref_req           = Bool(INPUT)
@@ -59,7 +65,7 @@ class vc707mig(implicit val p:Parameters) extends BlackBox
     //axi_s
     //slave interface write address ports
     val s_axi_awid            = Bits(INPUT,4)
-    val s_axi_awaddr          = Bits(INPUT,30)
+    val s_axi_awaddr          = Bits(INPUT,if(depth==oneGB) 30 else 32)
     val s_axi_awlen           = Bits(INPUT,8)
     val s_axi_awsize          = Bits(INPUT,3)
     val s_axi_awburst         = Bits(INPUT,2)
@@ -82,7 +88,7 @@ class vc707mig(implicit val p:Parameters) extends BlackBox
     val s_axi_bvalid          = Bool(OUTPUT)
     //slave interface read address ports
     val s_axi_arid            = Bits(INPUT,4)
-    val s_axi_araddr          = Bits(INPUT,30)
+    val s_axi_araddr          = Bits(INPUT,if(depth==oneGB) 30 else 32)
     val s_axi_arlen           = Bits(INPUT,8)
     val s_axi_arsize          = Bits(INPUT,3)
     val s_axi_arburst         = Bits(INPUT,2)