U500VC707DevKit 1-4GB support

[sifive-blocks.git] / src / main / scala / ip / xilinx / vc707mig / vc707mig.scala

diff --git a/src/main/scala/ip/xilinx/vc707mig/vc707mig.scala b/src/main/scala/ip/xilinx/vc707mig/vc707mig.scala
index 923956b450e5d9d5987c2262d3dd5d5da1c1a916..804062981937b8531e0739ed978ad80b95d6039f 100644 (file)
--- a/src/main/scala/ip/xilinx/vc707mig/vc707mig.scala
+++ b/src/main/scala/ip/xilinx/vc707mig/vc707mig.scala
@@ -2,16 +2,16 @@
 package sifive.blocks.ip.xilinx.vc707mig
 
 import Chisel._
-import config._
-import junctions._
+import chisel3.experimental.{Analog,attach}
+import freechips.rocketchip.util.GenericParameterizedBundle
+import freechips.rocketchip.config._
 
 // IP VLNV: xilinx.com:customize_ip:vc707mig:1.0
 // Black Box
-// Signals named _exactly_ as per MIG generated verilog
 
-trait VC707MIGUnidirectionalIODDR extends Bundle {
-  //outputs
-  val ddr3_addr             = Bits(OUTPUT,14)
+class VC707MIGIODDR(depth : BigInt) extends GenericParameterizedBundle(depth) {
+  require((depth<=0x100000000L),"VC707MIGIODDR supports upto 4GB depth configuraton")
+  val ddr3_addr             = Bits(OUTPUT,if(depth<=0x40000000L) 14 else 16)
   val ddr3_ba               = Bits(OUTPUT,3)
   val ddr3_ras_n            = Bool(OUTPUT)
   val ddr3_cas_n            = Bool(OUTPUT)
@@ -23,14 +23,17 @@ trait VC707MIGUnidirectionalIODDR extends Bundle {
   val ddr3_cs_n             = Bits(OUTPUT,1)
   val ddr3_dm               = Bits(OUTPUT,8)
   val ddr3_odt              = Bits(OUTPUT,1)
+
+  val ddr3_dq               = Analog(64.W)
+  val ddr3_dqs_n            = Analog(8.W)
+  val ddr3_dqs_p            = Analog(8.W)
 }
 
 //reused directly in io bundle for sifive.blocks.devices.xilinxvc707mig
-trait VC707MIGUnidirectionalIOClocksReset extends Bundle {
+trait VC707MIGIOClocksReset extends Bundle {
   //inputs
-  //differential system clocks
-  val sys_clk_n             = Bool(INPUT)
-  val sys_clk_p             = Bool(INPUT)
+  //"NO_BUFFER" clock source (must be connected to IBUF outside of IP)
+  val sys_clk_i             = Bool(INPUT)
   //user interface signals
   val ui_clk                = Clock(OUTPUT)
   val ui_clk_sync_rst       = Bool(OUTPUT)
@@ -43,16 +46,13 @@ trait VC707MIGUnidirectionalIOClocksReset extends Bundle {
 
 //scalastyle:off
 //turn off linter: blackbox name must match verilog module 
-class vc707mig(implicit val p:Parameters) extends BlackBox
+class vc707mig(depth : BigInt)(implicit val p:Parameters) extends BlackBox
 {
-  val io = new Bundle with VC707MIGUnidirectionalIODDR
-                      with VC707MIGUnidirectionalIOClocksReset {
-    // bidirectional signals on blackbox interface
-    // defined here as an output so "__inout" signal name does not have to be used
-    // verilog does not check the
-    val ddr3_dq               = Bits(OUTPUT,64)
-    val ddr3_dqs_n            = Bits(OUTPUT,8)
-    val ddr3_dqs_p            = Bits(OUTPUT,8)
+  require((depth<=0x100000000L),"vc707mig supports upto 4GB depth configuraton")
+
+  override def desiredName = if(depth<=0x40000000) "vc707mig" else "vc707mig4gb"
+
+  val io = new VC707MIGIODDR(depth) with VC707MIGIOClocksReset {
     // User interface signals
     val app_sr_req            = Bool(INPUT)
     val app_ref_req           = Bool(INPUT)
@@ -63,7 +63,7 @@ class vc707mig(implicit val p:Parameters) extends BlackBox
     //axi_s
     //slave interface write address ports
     val s_axi_awid            = Bits(INPUT,4)
-    val s_axi_awaddr          = Bits(INPUT,30)
+    val s_axi_awaddr          = Bits(INPUT,if(depth<=0x40000000) 30 else 32)
     val s_axi_awlen           = Bits(INPUT,8)
     val s_axi_awsize          = Bits(INPUT,3)
     val s_axi_awburst         = Bits(INPUT,2)
@@ -86,7 +86,7 @@ class vc707mig(implicit val p:Parameters) extends BlackBox
     val s_axi_bvalid          = Bool(OUTPUT)
     //slave interface read address ports
     val s_axi_arid            = Bits(INPUT,4)
-    val s_axi_araddr          = Bits(INPUT,30)
+    val s_axi_araddr          = Bits(INPUT,if(depth<=0x40000000) 30 else 32)
     val s_axi_arlen           = Bits(INPUT,8)
     val s_axi_arsize          = Bits(INPUT,3)
     val s_axi_arburst         = Bits(INPUT,2)