Refactor package hierarchy.

[sifive-blocks.git] / src / main / scala / util / Timer.scala

diff --git a/src/main/scala/util/Timer.scala b/src/main/scala/util/Timer.scala
index e0cba874f171b5acbfc464e1edea3a8d123035ae..52bbab2de251e20a1248372eebbf3e6efced2e41 100644 (file)
--- a/src/main/scala/util/Timer.scala
+++ b/src/main/scala/util/Timer.scala
@@ -3,8 +3,8 @@ package sifive.blocks.util
 
 import Chisel._
 import Chisel.ImplicitConversions._
-import regmapper._
-import util.WideCounter
+import freechips.rocketchip.regmapper._
+import freechips.rocketchip.util.WideCounter
 
 class SlaveRegIF(w: Int) extends Bundle {
   val write = Valid(UInt(width = w)).flip