+# SPDX-License-Identifier: LGPL-3-or-later
"""
This work is funded through NLnet under Grant 2019-02-012
else:
reg = Signal.like(incoming, name=name)
m.d.comb += outgoing.eq(Mux(settrue, incoming, reg))
- with m.If(settrue): # pass in some kind of expression/condition here
+ with m.If(settrue): # pass in some kind of expression/condition here
m.d.sync += reg.eq(incoming) # latch input into register
return reg
self.llen = llen
s_n, r_n = mkname("s", name), mkname("r", name)
q_n, qn_n = mkname("q", name), mkname("qn", name)
+ qint = mkname("qint", name)
qlq_n = mkname("qlq", name)
self.s = Signal(llen, name=s_n, reset=0)
- self.r = Signal(llen, name=r_n, reset=(1<<llen)-1) # defaults to off
+ self.r = Signal(llen, name=r_n, reset=(1 << llen)-1) # defaults to off
self.q = Signal(llen, name=q_n, reset_less=True)
self.qn = Signal(llen, name=qn_n, reset_less=True)
self.qlq = Signal(llen, name=qlq_n, reset_less=True)
+ self.q_int = Signal(llen, name=qint, reset_less=True)
def elaborate(self, platform):
m = Module()
- q_int = Signal(self.llen)
- m.d.sync += q_int.eq((q_int & ~self.r) | self.s)
+ next_o = Signal(self.llen, reset_less=True)
+ m.d.comb += next_o.eq((self.q_int & ~self.r) | self.s)
+ m.d.sync += self.q_int.eq(next_o)
if self.sync:
- m.d.comb += self.q.eq(q_int)
+ m.d.comb += self.q.eq(self.q_int)
else:
- m.d.comb += self.q.eq((q_int & ~self.r) | self.s)
+ m.d.comb += self.q.eq(next_o)
m.d.comb += self.qn.eq(~self.q)
- m.d.comb += self.qlq.eq(self.q | q_int) # useful output
+ m.d.comb += self.qlq.eq(self.q | self.q_int) # useful output
return m
yield
yield
+
def test_sr():
dut = SRLatch(llen=4)
vl = rtlil.convert(dut, ports=dut.ports())
run_simulation(dut, sr_sim(dut), vcd_name='test_srlatch_async.vcd')
+
if __name__ == '__main__':
test_sr()