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[nmutil.git] / src / nmutil / queue.py

diff --git a/src/nmutil/queue.py b/src/nmutil/queue.py
index ec592c83a56e8ea3e7416163dce28d9c1615d9da..36512024ff7c1ed26b22eb957c40de2e1409469c 100644 (file)
--- a/src/nmutil/queue.py
+++ b/src/nmutil/queue.py
@@ -23,8 +23,7 @@
 # TO PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR
 # MODIFICATIONS.
 
-from nmigen.compat.fhdl.specials import Memory
-from nmigen import Module, Signal, Mux, Elaboratable
+from nmigen import Module, Signal, Mux, Elaboratable, Memory
 from nmigen.utils import bits_for
 from nmigen.cli import main
 from nmigen.lib.fifo import FIFOInterface
@@ -62,8 +61,8 @@ class Queue(FIFOInterface, Elaboratable):
         m = Module()
 
         # set up an SRAM.  XXX bug in Memory: cannot create SRAM of depth 1
-        ram = Memory(self.width, self.depth if self.depth > 1 else 2)
-        m.submodules.ram = ram
+        ram = Memory(width=self.width,
+                     depth=self.depth if self.depth > 1 else 2)
         m.submodules.ram_read = ram_read = ram.read_port(domain="comb")
         m.submodules.ram_write = ram_write = ram.write_port()
 
@@ -74,17 +73,19 @@ class Queue(FIFOInterface, Elaboratable):
         # deq is "dequeue" (data out, aka "next stage")
         p_o_ready = self.w_rdy
         p_i_valid = self.w_en
-        enq_data = self.w_data # aka p_data_i
+        enq_data = self.w_data  # aka p_i_data
 
         n_o_valid = self.r_rdy
         n_i_ready = self.r_en
-        deq_data = self.r_data # aka n_data_o
+        deq_data = self.r_data  # aka n_o_data
 
         # intermediaries
         ptr_width = bits_for(self.depth - 1) if self.depth > 1 else 0
-        enq_ptr = Signal(ptr_width) # cyclic pointer to "insert" point (wrport)
-        deq_ptr = Signal(ptr_width) # cyclic pointer to "remove" point (rdport)
-        maybe_full = Signal() # not reset_less (set by sync)
+        # cyclic pointer to "insert" point (wrport)
+        enq_ptr = Signal(ptr_width)
+        # cyclic pointer to "remove" point (rdport)
+        deq_ptr = Signal(ptr_width)
+        maybe_full = Signal()  # not reset_less (set by sync)
 
         # temporaries
         do_enq = Signal(reset_less=True)
@@ -96,17 +97,17 @@ class Queue(FIFOInterface, Elaboratable):
         enq_max = Signal(reset_less=True)
         deq_max = Signal(reset_less=True)
 
-        m.d.comb += [ptr_match.eq(enq_ptr == deq_ptr), # read-ptr = write-ptr
+        m.d.comb += [ptr_match.eq(enq_ptr == deq_ptr),  # read-ptr = write-ptr
                      ptr_diff.eq(enq_ptr - deq_ptr),
                      enq_max.eq(enq_ptr == self.depth - 1),
                      deq_max.eq(deq_ptr == self.depth - 1),
                      empty.eq(ptr_match & ~maybe_full),
                      full.eq(ptr_match & maybe_full),
-                     do_enq.eq(p_o_ready & p_i_valid), # write conditions ok
-                     do_deq.eq(n_i_ready & n_o_valid), # read conditions ok
+                     do_enq.eq(p_o_ready & p_i_valid),  # write conditions ok
+                     do_deq.eq(n_i_ready & n_o_valid),  # read conditions ok
 
                      # set r_rdy and w_rdy (NOTE: see pipe mode below)
-                     n_o_valid.eq(~empty), # cannot read if empty!
+                     n_o_valid.eq(~empty),  # cannot read if empty!
                      p_o_ready.eq(~full),  # cannot write if full!
 
                      # set up memory and connect to input and output
@@ -114,8 +115,9 @@ class Queue(FIFOInterface, Elaboratable):
                      ram_write.data.eq(enq_data),
                      ram_write.en.eq(do_enq),
                      ram_read.addr.eq(deq_ptr),
-                     deq_data.eq(ram_read.data) # NOTE: overridden in fwft mode
-                    ]
+                     # NOTE: overridden in fwft mode
+                     deq_data.eq(ram_read.data)
+                     ]
 
         # under write conditions, SRAM write-pointer moves on next clock
         with m.If(do_enq):