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[nmutil.git] / src / nmutil / queue.py

diff --git a/src/nmutil/queue.py b/src/nmutil/queue.py
index f205e4710990bdd310033b5a34c459d44c3c4376..36512024ff7c1ed26b22eb957c40de2e1409469c 100644 (file)
--- a/src/nmutil/queue.py
+++ b/src/nmutil/queue.py
@@ -23,8 +23,7 @@
 # TO PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR
 # MODIFICATIONS.
 
-from nmigen.compat.fhdl.specials import Memory
-from nmigen import Module, Signal, Mux, Elaboratable
+from nmigen import Module, Signal, Mux, Elaboratable, Memory
 from nmigen.utils import bits_for
 from nmigen.cli import main
 from nmigen.lib.fifo import FIFOInterface
@@ -62,8 +61,8 @@ class Queue(FIFOInterface, Elaboratable):
         m = Module()
 
         # set up an SRAM.  XXX bug in Memory: cannot create SRAM of depth 1
-        ram = Memory(self.width, self.depth if self.depth > 1 else 2)
-        m.submodules.ram = ram
+        ram = Memory(width=self.width,
+                     depth=self.depth if self.depth > 1 else 2)
         m.submodules.ram_read = ram_read = ram.read_port(domain="comb")
         m.submodules.ram_write = ram_write = ram.write_port()