speed up ==, hash, <, >, <=, and >= for plain_data

[nmutil.git] / src / nmutil / sim_util.py

diff --git a/src/nmutil/sim_util.py b/src/nmutil/sim_util.py
index 9484eb4ab7bf619226689576ffac56a6be389c2d..d5678c2475a1730f437aa3c5c64838e92470fcaf 100644 (file)
--- a/src/nmutil/sim_util.py
+++ b/src/nmutil/sim_util.py
@@ -6,8 +6,11 @@
 
 from contextlib import contextmanager
 from hashlib import sha256
+
+from nmigen.hdl.ir import Fragment, ClockDomain
 from nmutil.get_test_path import get_test_path
 from nmigen.sim import Simulator
+from nmigen.back.rtlil import convert
 
 
 def hash_256(v):
@@ -17,11 +20,24 @@ def hash_256(v):
     )
 
 
-@contextmanager
-def do_sim(test_case, dut, traces=()):
-    sim = Simulator(dut)
+def write_il(test_case, dut, ports=()):
+    # only elaborate once, cuz users' stupid code breaks if elaborating twice
+    dut = Fragment.get(dut, platform=None)
+    if "sync" not in dut.domains:
+        dut.add_domains(ClockDomain("sync"))
     path = get_test_path(test_case, "sim_test_out")
     path.parent.mkdir(parents=True, exist_ok=True)
+    il_path = path.with_suffix(".il")
+    il_path.write_text(convert(dut, ports=ports), encoding="utf-8")
+    return dut, path
+
+
+@contextmanager
+def do_sim(test_case, dut, traces=(), ports=None):
+    if ports is None:
+        ports = traces
+    dut, path = write_il(test_case, dut, ports)
+    sim = Simulator(dut)
     vcd_path = path.with_suffix(".vcd")
     gtkw_path = path.with_suffix(".gtkw")
     with sim.write_vcd(vcd_path.open("wt", encoding="utf-8"),