import BUtils ::*;
import AXI4_Lite_Types::*;
- interface Ifc_rgbttl_dummy()
+ interface Ifc_rgbttl_dummy;
interface AXI4_Lite_Slave_IFC#(`ADDR, `DATA, `USERSPACE) slave;
method Bit#(1) de;
method Bit#(1) ck;
endinterface
(*synthesize*)
- module mkrgbttl_dummy(Ifc_rgbttl_dummy)
+ module mkrgbttl_dummy(Ifc_rgbttl_dummy);
AXI4_Lite_Slave_Xactor_IFC#(`ADDR,`DATA, `USERSPACE)
s_xactor<-mkAXI4_Lite_Slave_Xactor();
let v_buswidth = valueOf(v_buswidth);