from copy import deepcopy
+
class Pinouts(object):
def __init__(self):
self.pins = {}
self.fnspec = {}
def has_key(self, k):
- return self.pins.has_key(k)
+ return k in self.pins
def add_spec(self, k, v):
self.fnspec[k] = v
def update(self, pinidx, v):
- if not self.pins.has_key(pinidx):
+ if pinidx not in self.pins:
self.pins[pinidx] = v
else:
self.pins[pinidx].update(v)
def __delitem__(self, k):
del self.pins[k]
+ def __getitem__(self, k):
+ return self.pins[k]
+
class Pins(object):
def __init__(self, fname, pingroup, bankspec, suffix, offs, bank, mux,
- spec=None, limit=None, origsuffix=None):
+ spec=None, limit=None, origsuffix=None):
+
+ # function type can be in, out or inout, represented by - + *
+ # strip function type out of each pin name
+ self.fntype = {}
+ for i in range(len(pingroup)):
+ pname = pingroup[i]
+ if not pname:
+ continue
+ fntype = pname[-1]
+ if fntype not in '+-*':
+ continue
+ pname = pname[:-1]
+ fntype = {'-': 'in', '+': 'out', '*': 'inout'}[fntype]
+ self.fntype[pname] = fntype
+ pingroup[i] = pname
+
self.fname = fname
self.pingroup = pingroup
self.bankspec = bankspec
self.bank = bank
self.mux = mux
+ # create consistent name suffixes
pingroup = namesuffix(fname, suffix, pingroup)
- suffix = ''
+ suffix = '' # hack
res = {}
names = {}
name_ = "%s_%s" % (name, suffix)
else:
name_ = name
- if spec and spec.has_key(name):
+ if spec and name in spec:
continue
pin = {mux: (name_, bank)}
offs_bank, offs_ = offs
name_ = name
if not spec:
continue
- if not spec.has_key(name):
+ if name not in spec:
continue
idx_, mux_, bank_ = spec[name]
idx_ = names[idx_]
pin = {mux_: (name_, bank_)}
- if res.has_key(idx_):
+ if idx_ in res:
res[idx_].update(pin)
else:
res[idx_] = pin
def i2s(bankspec, suffix, offs, bank, mux=1, spec=None, limit=None):
- i2spins = ['MCK', 'BCK', 'LRCK', 'DI']
- for i in range(4):
- i2spins.append("DO%d" % i)
+ i2spins = ['MCK+', 'BCK+', 'LRCK+', 'DI-', 'DO+']
+ # for i in range(4):
+ # i2spins.append("DO%d+" % i)
return Pins('IIS', i2spins, bankspec, suffix, offs, bank, mux, spec, limit,
origsuffix=suffix)
+
def emmc(bankspec, suffix, offs, bank, mux=1, spec=None):
- emmcpins = ['CMD', 'CLK']
+ emmcpins = ['CMD+', 'CLK+']
for i in range(8):
- emmcpins.append("D%d" % i)
+ emmcpins.append("D%d*" % i)
return Pins('MMC', emmcpins, bankspec, suffix, offs, bank, mux, spec,
origsuffix=suffix)
+
def sdmmc(bankspec, suffix, offs, bank, mux=1, spec=None,
- start=None, limit=None):
- sdmmcpins = ['CMD', 'CLK']
+ start=None, limit=None):
+ sdmmcpins = ['CMD+', 'CLK+']
for i in range(4):
- sdmmcpins.append("D%d" % i)
+ sdmmcpins.append("D%d*" % i)
sdmmcpins = sdmmcpins[start:limit]
return Pins('SD', sdmmcpins, bankspec, suffix, offs, bank, mux, spec,
origsuffix=suffix)
+
def spi(bankspec, suffix, offs, bank, mux=1, spec=None):
- spipins = ['CLK', 'NSS', 'MOSI', 'MISO', 'NSS']
+ spipins = ['CLK*', 'NSS*', 'MOSI*', 'MISO*']
return Pins('SPI', spipins, bankspec, suffix, offs, bank, mux, spec,
origsuffix=suffix)
+
def quadspi(bankspec, suffix, offs, bank, mux=1, spec=None, limit=None):
- spipins = ['CK', 'NSS', 'IO0', 'IO1', 'IO2', 'IO3']
- return Pins('QSPI', spipins, bankspec, suffix, offs, bank, mux, spec, limit,
- origsuffix=suffix)
+ spipins = ['CK*', 'NSS*', 'IO0*', 'IO1*', 'IO2*', 'IO3*']
+ return Pins(
+ 'QSPI',
+ spipins,
+ bankspec,
+ suffix,
+ offs,
+ bank,
+ mux,
+ spec,
+ limit,
+ origsuffix=suffix)
+
def i2c(bankspec, suffix, offs, bank, mux=1, spec=None):
- spipins = ['SDA', 'SCL']
+ spipins = ['SDA*', 'SCL*']
return Pins('TWI', spipins, bankspec, suffix, offs, bank, mux, spec,
origsuffix=suffix)
+
def jtag(bankspec, suffix, offs, bank, mux=1, spec=None):
- uartpins = ['MS', 'DI', 'DO', 'CK']
- return Pins('JTAG', uartpins, bankspec, suffix, offs, bank, mux, spec,
+ jtagpins = ['MS+', 'DI-', 'DO+', 'CK+']
+ return Pins('JTAG', jtagpins, bankspec, suffix, offs, bank, mux, spec,
origsuffix=suffix)
+
def uart(bankspec, suffix, offs, bank, mux=1, spec=None):
- uartpins = ['TX', 'RX']
+ uartpins = ['TX+', 'RX-']
return Pins('UART', uartpins, bankspec, suffix, offs, bank, mux, spec,
origsuffix=suffix)
+
def namesuffix(name, suffix, namelist):
names = []
for n in namelist:
names.append("%s_%s" % (name, suffix))
return names
+
def ulpi(bankspec, suffix, offs, bank, mux=1, spec=None):
- ulpipins = ['CK', 'DIR', 'STP', 'NXT']
+ ulpipins = ['CK+', 'DIR+', 'STP+', 'NXT+']
for i in range(8):
- ulpipins.append('D%d' % i)
+ ulpipins.append('D%d*' % i)
return Pins('ULPI', ulpipins, bankspec, suffix, offs, bank, mux, spec,
origsuffix=suffix)
+
def uartfull(bankspec, suffix, offs, bank, mux=1, spec=None):
- uartpins = ['TX', 'RX', 'CTS', 'RTS']
+ uartpins = ['TX+', 'RX-', 'CTS-', 'RTS+']
return Pins('UARTQ', uartpins, bankspec, suffix, offs, bank, mux, spec,
origsuffix=suffix)
+
def rgbttl(bankspec, suffix, offs, bank, mux=1, spec=None):
- ttlpins = ['CK', 'DE', 'HS', 'VS']
+ ttlpins = ['CK+', 'DE+', 'HS+', 'VS+']
for i in range(24):
- ttlpins.append("D%d" % i)
+ ttlpins.append("D%d+" % i)
return Pins('LCD', ttlpins, bankspec, suffix, offs, bank, mux, spec,
origsuffix=suffix)
+
def rgmii(bankspec, suffix, offs, bank, mux=1, spec=None):
buspins = []
for i in range(4):
- buspins.append("ERXD%d" % i)
+ buspins.append("ERXD%d-" % i)
for i in range(4):
- buspins.append("ETXD%d" % i)
- buspins += ['ERXCK', 'ERXERR', 'ERXDV',
- 'EMDC', 'EMDIO',
- 'ETXEN', 'ETXCK', 'ECRS',
- 'ECOL', 'ETXERR']
+ buspins.append("ETXD%d+" % i)
+ buspins += ['ERXCK-', 'ERXERR-', 'ERXDV-',
+ 'EMDC+', 'EMDIO*',
+ 'ETXEN+', 'ETXCK+', 'ECRS-',
+ 'ECOL+', 'ETXERR+']
return Pins('RG', buspins, bankspec, suffix, offs, bank, mux, spec,
origsuffix=suffix)
+
def flexbus1(bankspec, suffix, offs, bank, mux=1, spec=None, limit=None):
buspins = []
for i in range(8):
- buspins.append("AD%d" % i)
+ buspins.append("AD%d*" % i)
for i in range(2):
- buspins.append("CS%d" % i)
- buspins += ['ALE', 'OE', 'RW', 'TA', 'CLK',
+ buspins.append("CS%d+" % i)
+ buspins += ['ALE', 'OE', 'RW', 'TA', 'CLK+',
'A0', 'A1', 'TS', 'TBST',
'TSIZ0', 'TSIZ1']
for i in range(4):
buspins.append("BWE%d" % i)
- for i in range(2,6):
- buspins.append("CS%d" % i)
+ for i in range(2, 6):
+ buspins.append("CS%d+" % i)
return Pins('FB', buspins, bankspec, suffix, offs, bank, mux, spec, limit,
origsuffix=suffix)
+
def flexbus2(bankspec, suffix, offs, bank, mux=1, spec=None, limit=None):
buspins = []
- for i in range(8,32):
- buspins.append("AD%d" % i)
+ for i in range(8, 32):
+ buspins.append("AD%d*" % i)
return Pins('FB', buspins, bankspec, suffix, offs, bank, mux, spec, limit,
origsuffix=suffix)
+
def sdram1(bankspec, suffix, offs, bank, mux=1, spec=None):
buspins = []
for i in range(16):
- buspins.append("SDRDQM%d" % i)
+ buspins.append("SDRDQM%d*" % i)
for i in range(12):
- buspins.append("SDRAD%d" % i)
+ buspins.append("SDRAD%d+" % i)
for i in range(8):
- buspins.append("SDRDQ%d" % i)
+ buspins.append("SDRDQ%d+" % i)
for i in range(3):
- buspins.append("SDRCS%d#" % i)
+ buspins.append("SDRCS%d#+" % i)
for i in range(2):
- buspins.append("SDRDQ%d" % i)
+ buspins.append("SDRDQ%d+" % i)
for i in range(2):
- buspins.append("SDRBA%d" % i)
- buspins += ['SDRCKE', 'SDRRAS#', 'SDRCAS#', 'SDRWE#',
- 'SDRRST']
+ buspins.append("SDRBA%d+" % i)
+ buspins += ['SDRCKE+', 'SDRRAS#+', 'SDRCAS#+', 'SDRWE#+',
+ 'SDRRST+']
return Pins('SDR', buspins, bankspec, suffix, offs, bank, mux, spec,
origsuffix=suffix)
+
def sdram2(bankspec, suffix, offs, bank, mux=1, spec=None, limit=None):
buspins = []
- for i in range(3,6):
- buspins.append("SDRCS%d#" % i)
- for i in range(8,32):
- buspins.append("SDRDQ%d" % i)
+ for i in range(3, 6):
+ buspins.append("SDRCS%d#+" % i)
+ for i in range(8, 32):
+ buspins.append("SDRDQ%d*" % i)
return Pins('SDR', buspins, bankspec, suffix, offs, bank, mux, spec, limit,
origsuffix=suffix)
+
def mcu8080(bankspec, suffix, offs, bank, mux=1, spec=None):
buspins = []
for i in range(8):
- buspins.append("MCUD%d" % i)
+ buspins.append("MCUD%d*" % i)
for i in range(8):
- buspins.append("MCUAD%d" % (i+8))
+ buspins.append("MCUAD%d+" % (i + 8))
for i in range(6):
- buspins.append("MCUCS%d" % i)
+ buspins.append("MCUCS%d+" % i)
for i in range(2):
- buspins.append("MCUNRB%d" % i)
- buspins += ['MCUCD', 'MCURD', 'MCUWR', 'MCUCLE', 'MCUALE',
- 'MCURST']
+ buspins.append("MCUNRB%d+" % i)
+ buspins += ['MCUCD+', 'MCURD+', 'MCUWR+', 'MCUCLE+', 'MCUALE+',
+ 'MCURST+']
return Pins('MCU', buspins, bankspec, suffix, offs, bank, mux, spec,
origsuffix=suffix)
+
def _pinbank(bankspec, prefix, suffix, offs, bank, gpiooffs, gpionum=1, mux=1,
spec=None):
gpiopins = []
- for i in range(gpiooffs, gpiooffs+gpionum):
- gpiopins.append("%s%d" % (bank, i))
- return Pins('GPIO', gpiopins, bankspec, suffix, offs, bank, mux, spec,
+ for i in range(gpiooffs, gpiooffs + gpionum):
+ gpiopins.append("%s%d*" % (bank, i))
+ return Pins(prefix, gpiopins, bankspec, suffix, offs, bank, mux, spec,
origsuffix=suffix)
+
def eint(bankspec, suffix, offs, bank, gpiooffs, gpionum=1, mux=1, spec=None):
gpiopins = []
- for i in range(gpiooffs, gpiooffs+gpionum):
- gpiopins.append("%d" % (i))
+ for i in range(gpiooffs, gpiooffs + gpionum):
+ gpiopins.append("%d*" % (i))
return Pins('EINT', gpiopins, bankspec, suffix, offs, bank, mux, spec,
origsuffix=suffix)
-def pwm(bankspec, suffix, offs, bank, mux=1, spec=None):
- return Pins('PWM', ['', ], bankspec, suffix, offs, bank, mux, spec,
+
+def pwm(bankspec, suffix, offs, bank, pwmoffs, pwmnum=1, mux=1, spec=None):
+ pwmpins = []
+ for i in range(pwmoffs, pwmoffs + pwmnum):
+ pwmpins.append("%d+" % (i))
+ return Pins('PWM', pwmpins, bankspec, suffix, offs, bank, mux, spec,
origsuffix=suffix)
+
def gpio(bankspec, suffix, offs, bank, gpiooffs, gpionum=1, mux=1, spec=None):
- return _pinbank(bankspec, "GPIO", suffix, offs, bank, gpiooffs,
+ return _pinbank(bankspec, "GPIO%s" % bank, suffix, offs, bank, gpiooffs,
gpionum, mux=0, spec=None)
-def display(pins):
- print "| Pin | Mux0 | Mux1 | Mux2 | Mux3 |"
- print "| --- | ----------- | ----------- | ----------- | ----------- |"
- pinidx = pins.keys()
- pinidx.sort()
- for pin in pinidx:
- pdata = pins.get(pin)
- res = '| %3d |' % pin
- for mux in range(4):
- if not pdata.has_key(mux):
- res += " |"
- continue
- name, bank = pdata[mux]
- res += " %s %-9s |" % (bank, name)
- print res
-
-def fnsplit(f):
- a = ''
- n = 0
- if not f.startswith('FB_'):
- f2 = f.split('_')
- if len(f2) == 2:
- if f2[1].isdigit():
- return f2[0], int(f2[1])
- return f2[0], f2[1]
- #print f
- while f and not f[0].isdigit():
- a += f[0]
- f = f[1:]
- return a, int(f) if f else None
-
-def fnsort(f1, f2):
- a1, n1 = fnsplit(f1)
- a2, n2 = fnsplit(f2)
- x = cmp(a1, a2)
- if x != 0:
- return x
- return cmp(n1, n2)
-
-def find_fn(fname, names):
- for n in names:
- if fname.startswith(n):
- return n
-
-def display_fns(bankspec, pins, function_names):
- fn_names = function_names.keys()
- fns = {}
- for (pin, pdata) in pins.items():
- for mux in range(1,4): # skip GPIO for now
- if not pdata.has_key(mux):
- continue
- name, bank = pdata[mux]
- assert name != None, str(bank)
- if not fns.has_key(name):
- fns[name] = []
- fns[name].append((pin-bankspec[bank], mux, bank))
-
- fnidx = fns.keys()
- fnidx.sort(fnsort)
- current_fn = None
- for fname in fnidx:
- fnbase = find_fn(fname, fn_names)
- #print "name", fname, fnbase
- if fnbase != current_fn:
- if current_fn is not None:
- print
- print "## %s" % fnbase
- print
- print function_names[fnbase]
- print
- current_fn = fnbase
- print "* %-9s :" % fname,
- for (pin, mux, bank) in fns[fname]:
- print "%s%d/%d" % (bank, pin, mux),
- print
-
- return fns
-
-def check_functions(title, bankspec, fns, pins, required, eint, pwm,
- descriptions=None):
- fns = deepcopy(fns)
- pins = deepcopy(pins)
- if descriptions is None:
- descriptions = {}
-
- print "# Pinmap for %s" % title
- print
-
-
- for name in required:
- print "## %s" % name
- print
- if descriptions and descriptions.has_key(name):
- print descriptions[name]
- print
-
- name = name.split(':')
- if len(name) == 2:
- findbank = name[0][0]
- findmux = int(name[0][1:])
- name = name[1]
- else:
- name = name[0]
- findbank = None
- findmux = None
- name = name.split('/')
- if len(name) == 2:
- count = int(name[1])
- else:
- count = 100000
- name = name[0]
- found = set()
- fnidx = fns.keys()
- #fnidx.sort(fnsort)
- pinfound = {}
- for fname in fnidx:
- if not fname.startswith(name):
- continue
- for pin, mux, bank in fns[fname]:
- if findbank is not None:
- if findbank != bank:
- continue
- if findmux != mux:
- continue
- pin_ = pin + bankspec[bank]
- if pins.has_key(pin_):
- pinfound[pin_] = (fname, pin_, bank, pin, mux)
-
- pinidx = pinfound.keys()
- pinidx.sort()
-
- for pin_ in pinidx:
- fname, pin_, bank, pin, mux = pinfound[pin_]
- if fname in found:
- continue
- found.add(fname)
- if len(found) > count:
- continue
- del pins[pin_]
- print "* %s %d %s%d/%d" % (fname, pin_, bank, pin, mux)
-
- print
-
- # gpios
- gpios = []
- for name in descriptions.keys():
- if not name.startswith('GPIO'):
- continue
- if name == 'GPIO':
- continue
- gpios.append(name)
- gpios.sort()
-
- if gpios:
- print "## GPIO"
- print
-
- for fname in gpios:
- if fname in found:
- continue
- desc = ''
- if descriptions and descriptions.has_key(fname):
- desc = ': %s' % descriptions[fname]
- bank = fname[4]
- pin = int(fname[5:])
- pin_ = pin + bankspec[bank]
- if not pins.has_key(pin_):
- continue
- del pins[pin_]
- found.add(fname)
- print "* %-8s %d %s%-2d %s" % (fname, pin_, bank, pin, desc)
- print
-
- if eint:
- display_group(bankspec, "EINT", eint, fns, pins, descriptions)
- if pwm:
- display_group(bankspec, "PWM", pwm, fns, pins, descriptions)
-
- print "## Unused Pinouts (spare as GPIO) for '%s'" % title
- print
- if descriptions and descriptions.has_key('GPIO'):
- print descriptions['GPIO']
- print
- display(pins)
- print
-
- return pins # unused
-
-def display_group(bankspec, title, todisplay, fns, pins, descriptions):
- print "## %s" % title
- print
-
- found = set()
- for fname in todisplay:
- desc = ''
- if descriptions and descriptions.has_key(fname):
- desc = ': %s' % descriptions[fname]
- fname = fname.split(':')
- if len(fname) == 2:
- findbank = fname[0][0]
- findmux = int(fname[0][1:])
- fname = fname[1]
- else:
- fname = fname[0]
- findbank = None
- findmux = None
- for (pin, mux, bank) in fns[fname]:
- if findbank is not None:
- if findbank != bank:
- continue
- if findmux != mux:
- continue
- if fname in found:
- continue
- pin_ = pin + bankspec[bank]
- if not pins.has_key(pin_):
- continue
- del pins[pin_]
- found.add(fname)
- print "* %s %d %s%d/%d %s" % (fname, pin_, bank, pin, mux, desc)
- print
def pinmerge(pins, fn):
# hack, store the function specs in the pins dict
pins.fnspec = pins
if fname == 'GPIO':
fname = fname + bank
- assert not pins.has_key('EINT')
- if not pins.fnspec.has_key(fname):
+ assert 'EINT' not in pins
+ if fname not in pins.fnspec:
pins.add_spec(fname, {})
print "fname bank suffix", fname, bank, suffix
if suffix or fname == 'EINT' or fname == 'PWM':
specname = fname + suffix
else:
specname = fname + bank
- pins.fnspec[fname][specname] = fn
-
+ if specname in pins.fnspec[fname]:
+ # ok so some declarations may bring in different
+ # names at different stages (EINT, PWM, flexbus1/2)
+ # so we have to merge the names in. main thing is
+ # the pingroup
+ tomerge = pins.fnspec[fname][specname]
+ for p in fn.pingroup:
+ if p not in tomerge.pingroup:
+ tomerge.pingroup.append(p)
+ tomerge.pins.update(fn.pins)
+ tomerge.fntype.update(fn.fntype)
+ else:
+ pins.fnspec[fname][specname] = deepcopy(fn)
# merge actual pins
for (pinidx, v) in fn.pins.items():
- print "pinidx", pinidx
pins.update(pinidx, v)
-
-def display_fixed(fixed, offs):
-
- fkeys = fixed.keys()
- fkeys.sort()
- pin_ = offs
- for pin, k in enumerate(fkeys):
- print "## %s" % k
- print
- prevname = ''
- linecount = 0
- for name in fixed[k]:
- if linecount == 4:
- linecount = 0
- print
- if prevname[:2] == name[:2] and linecount != 0:
- print name,
- linecount += 1
- else:
- if linecount != 0:
- print
- print "* %d: %d %s" % (pin_, pin, name),
- linecount = 1
- prevname = name
- pin_ += 1
- if linecount != 0:
- print
- print
-
projects / pinmux.git / blobdiff