Modified for use with pinmux, will probably change the class name later.
"""
from random import randint
-from math import ceil, floor
+#from math import ceil, floor
from nmigen import Elaboratable, Module, Signal, Record, Array, Cat
from nmigen.hdl.rec import Layout
from nmigen.utils import log2_int
from nmigen.cli import rtlil
-from soc.minerva.wishbone import make_wb_layout
+#from soc.minerva.wishbone import make_wb_layout
from nmutil.util import wrap
-from soc.bus.test.wb_rw import wb_read, wb_write
+#from soc.bus.test.wb_rw import wb_read, wb_write
from nmutil.gtkw import write_gtkw
cxxsim = False
if cxxsim:
- from nmigen.sim.cxxsim import Simulator, Settle
+ from nmigen.sim.cxxsim import Simulator, Settle, Delay
else:
- from nmigen.sim import Simulator, Settle
+ from nmigen.sim import Simulator, Settle, Delay
io_layout = (("i", 1),
("oe", 1),
#b1 = self.b1
out_port = self.out_port
- sync += out_port.o.eq(bank_ports[0].o)
- sync += out_port.oe.eq(bank_ports[0].oe)
- sync += bank_ports[0].i.eq(out_port.i)
-
# Connect IO Pad output port to one of the peripheral IOs
# Connect peripheral inputs to the IO pad input
with m.Switch(bank):
with m.Case(BANK0_WB):
- self.connect_bank_to_io(sync, BANK0_WB)
+ self.connect_bank_to_io(comb, BANK0_WB)
with m.Case(BANK1_P1):
- self.connect_bank_to_io(sync, BANK1_P1)
+ self.connect_bank_to_io(comb, BANK1_P1)
with m.Case(BANK2_P2):
- self.connect_bank_to_io(sync, BANK2_P2)
+ self.connect_bank_to_io(comb, BANK2_P2)
with m.Case(BANK3_P3):
- self.connect_bank_to_io(sync, BANK3_P3)
+ self.connect_bank_to_io(comb, BANK3_P3)
return m
def connect_bank_to_io(self, domain, bank_arg):
domain += self.out_port.oe.eq(self.bank_ports[bank_arg].oe)
domain += self.bank_ports[bank_arg].i.eq(self.out_port.i)
- temp_list = list(range(self.n_banks))
- temp_list.pop(temp_list.index(bank_arg))
- print("Banks with input hardwired to 0: {}".format(temp_list))
- for j in range(len(temp_list)):
- unused_bank = temp_list[j]
- domain += self.bank_ports[unused_bank].i.eq(0)
+ # unnecessary, yosys correctly converted to mux's already
+ #temp_list = list(range(self.n_banks))
+ #temp_list.pop(temp_list.index(bank_arg))
+ #print("Banks with input hardwired to 0: {}".format(temp_list))
+ #for j in range(len(temp_list)):
+ # unused_bank = temp_list[j]
+ # domain += self.bank_ports[unused_bank].i.eq(0)
def __iter__(self):
""" Get member signals for Verilog form. """
m.submodules.pinmux = dut
sim = Simulator(m)
- sim.add_clock(1e-6)
+ #sim.add_clock(1e-6)
- sim.add_sync_process(wrap(test_iomux(dut)))
+ #sim.add_sync_process(wrap(test_iomux(dut)))
+ sim.add_process(wrap(test_iomux(dut)))
sim_writer = sim.write_vcd(filename+".vcd")
with sim_writer:
sim.run()
gen_gtkw_doc("top.pinmux", dut.n_banks, filename)
+# Method for toggling i/o/oe of a particular bank port,
+# while bank_sel has three different values:
+# value before, given value, value after
+# when rand is True, previous and consecutive values are
+# random (but NOT equal to given bank_sel)
+def test_single_bank(dut, bank, rand=True):
+ if rand:
+ print("Randomising the prev and next banks")
+ prev_bank=bank
+ while(prev_bank == bank):
+ prev_bank = randint(0, dut.n_banks-1)
+ next_bank=bank
+ while(next_bank == bank):
+ next_bank = randint(0, dut.n_banks-1)
+ else:
+ if bank == 0:
+ prev_bank = dut.n_banks
+ else:
+ prev_bank = bank - 1
+
+ if bank == dut.n_banks:
+ next_bank = 0
+ else:
+ next_bank = bank + 1
+
+ print("Prev={}, Given={}, Next={}".format(prev_bank, bank, next_bank))
+
+ yield dut.bank.eq(prev_bank)
+ yield Delay(1e-6)
+ yield dut.bank_ports[bank].o.eq(0)
+ yield dut.bank_ports[bank].oe.eq(0)
+ yield dut.out_port.i.eq(0)
+ yield Delay(1e-6)
+
+ yield dut.bank.eq(bank)
+ yield Delay(1e-6)
+
+ test_o = yield dut.out_port.o
+ test_oe = yield dut.out_port.oe
+ test_i = yield dut.bank_ports[bank].i
+ assert(test_o == 0)
+ assert(test_oe == 0)
+ assert(test_i == 0)
+
+ yield dut.bank_ports[bank].o.eq(1)
+ yield Delay(1e-6)
+ yield dut.bank_ports[bank].oe.eq(1)
+ yield Delay(1e-6)
+ yield dut.out_port.i.eq(1)
+ yield Delay(1e-6)
+
+ test_o = yield dut.out_port.o
+ test_oe = yield dut.out_port.oe
+ test_i = yield dut.bank_ports[bank].i
+ #print(test_o, test_oe, test_i)
+ assert(test_o == 1)
+ assert(test_oe == 1)
+ assert(test_i == 1)
+
+ yield dut.bank.eq(next_bank)
+ yield Delay(1e-6)
+ yield dut.bank_ports[bank].o.eq(0)
+ yield dut.bank_ports[bank].oe.eq(0)
+ yield dut.out_port.i.eq(0)
+ yield Delay(1e-6)
+
def test_iomux(dut):
print("------START----------------------")
#print(dir(dut.bank_ports[0]))
#print(dut.bank_ports[0].fields)
# TODO: turn into methods
- yield dut.bank_ports[0].o.eq(1)
- yield dut.bank.eq(0)
- yield
- yield dut.bank_ports[0].o.eq(1)
- yield
- yield dut.bank_ports[1].o.eq(1)
- yield
- yield dut.bank_ports[0].oe.eq(1)
- yield
- yield dut.bank.eq(1)
- yield
-
- yield dut.bank_ports[0].o.eq(0)
- yield
- yield dut.bank_ports[1].o.eq(0)
- yield
- yield dut.bank_ports[1].oe.eq(1)
- yield
- yield dut.bank.eq(0)
- yield
-
- yield dut.bank.eq(1)
- yield
- yield dut.bank_ports[1].o.eq(1)
- yield
- yield dut.bank_ports[2].o.eq(1)
- yield
- yield dut.bank_ports[1].oe.eq(1)
- yield
- yield dut.bank.eq(2)
- yield
-
- yield dut.bank_ports[1].o.eq(0)
- yield
- yield dut.bank_ports[2].o.eq(0)
- yield
- yield dut.bank_ports[2].oe.eq(1)
- yield
- yield dut.bank.eq(0)
- yield
+ yield from test_single_bank(dut, 0)
+ yield from test_single_bank(dut, 1)
+ yield from test_single_bank(dut, 2)
+ yield from test_single_bank(dut, 3)
print("Finished the 1-bit IO mux block test!")
projects / pinmux.git / blobdiff