redo JTAG to not use Pins clas, it is by pinspec

[pinmux.git] / src / spec / jtag.py

diff --git a/src/spec/jtag.py b/src/spec/jtag.py
index 4b4f17a97d672c3f22b668008a1c058ac2500da6..efda2806c07e6f01f3e8501e9bcdd8245fc63991 100644 (file)
--- a/src/spec/jtag.py
+++ b/src/spec/jtag.py
@@ -6,9 +6,7 @@ using Staf Verhaegen (Chips4Makers) wishbone TAP
 from collections import OrderedDict
 from nmigen import (Module, Signal, Elaboratable, Cat)
 from nmigen.cli import rtlil
-from c4m.nmigen.jtag.tap import IOType
-from soc.debug.dmi import  DMIInterface, DBGCore
-from soc.debug.dmi2jtag import DMITAP
+from c4m.nmigen.jtag.tap import IOType, TAP
 
 # map from pinmux to c4m jtag iotypes
 iotypes = {'-': IOType.In,
@@ -17,6 +15,12 @@ iotypes = {'-': IOType.In,
            '*': IOType.InTriOut,
         }
 
+resiotypes = {'i': IOType.In,
+           'o': IOType.Out,
+           'oe': IOType.TriOut,
+           'io': IOType.InTriOut,
+        }
+
 scanlens = {IOType.In: 1,
            IOType.Out: 1,
            IOType.TriOut: 2,
@@ -32,13 +36,16 @@ def dummy_pinset():
              'gpio': gpios,
              'i2c': ['sda*', 'scl+']}
 
+
 # TODO: move to suitable location
 class Pins:
     """declare a list of pins, including name and direction.  grouped by fn
     the pin dictionary needs to be in a reliable order so that the JTAG
     Boundary Scan is also in a reliable order
     """
-    def __init__(self, pindict):
+    def __init__(self, pindict=None):
+        if pindict is None:
+            pindict = {}
         self.io_names = OrderedDict()
         if isinstance(pindict, OrderedDict):
             self.io_names.update(pindict)
@@ -61,22 +68,22 @@ class Pins:
                 scan_idx += scanlens[iotype] # inc boundary reg scan offset
 
 
-class JTAG(DMITAP, Pins):
+class JTAG(TAP, Pins):
     # 32-bit data width here so that it matches with litex
     def __init__(self, pinset, domain, wb_data_wid=32):
         self.domain = domain
-        DMITAP.__init__(self, ir_width=4)
+        TAP.__init__(self, ir_width=4)
         Pins.__init__(self, pinset)
 
         # enumerate pin specs and create IOConn Records.
         # we store the boundary scan register offset in the IOConn record
-        self.ios = [] # these are enumerated in external_ports
+        self.ios = {} # these are enumerated in external_ports
         self.scan_len = 0
         for fn, pin, iotype, pin_name, scan_idx in list(self):
             io = self.add_io(iotype=iotype, name=pin_name)
             io._scan_idx = scan_idx # hmm shouldn't really do this
             self.scan_len += scan_idx # record full length of boundary scan
-            self.ios.append(io)
+            self.ios[pin_name] = io
 
         # this is redundant.  or maybe part of testing, i don't know.
         self.sr = self.add_shiftreg(ircode=4, length=3,
@@ -127,7 +134,7 @@ class JTAG(DMITAP, Pins):
         """
         ports = super().external_ports()           # gets JTAG signal names
         ports += list(self.wb.fields.values())     # wishbone signals
-        for io in self.ios:
+        for io in self.ios.values():
             ports += list(io.core.fields.values()) # io "core" signals
             ports += list(io.pad.fields.values())  # io "pad" signals"
         return ports
@@ -135,7 +142,7 @@ class JTAG(DMITAP, Pins):
 
 if __name__ == '__main__':
     pinset = dummy_pinset()
-    dut = JTAG(pinset)
+    dut = JTAG(pinset, "sync")
 
     vl = rtlil.convert(dut)
     with open("test_jtag.il", "w") as f: