ps = PinSpec(pinbanks, fixedpins, function_names)
- ps.vdd("E", ('S', 0), 0, 0, 1)
- ps.vss("E", ('S', 1), 0, 0, 1)
- ps.vdd("I", ('S', 2), 0, 0, 1)
- ps.vss("I", ('S', 3), 0, 0, 1)
- ps.sdram1("", ('S', 4), 0, 0, 21)
- ps.mi2c("", ('S', 26), 0, 0, 2)
- ps.vss("I", ('S', 28), 0, 1, 1)
- ps.vdd("I", ('S', 29), 0, 1, 1)
- ps.vss("E", ('S', 30), 0, 1, 1)
- ps.vdd("E", ('S', 31), 0, 1, 1)
+ ps.sdram1("", ('W', 0), 0, 15, 6, rev=True) # AD4-9, turned round
+ ps.vdd("E", ('W', 6), 0, 0, 1)
+ ps.vss("E", ('W', 7), 0, 0, 1)
+ ps.vdd("I", ('W', 8), 0, 0, 1)
+ ps.vss("I", ('W', 9), 0, 0, 1)
+ ps.sdram1("", ('W', 10), 0, 0, 15, rev=True) # SDRAM DAM0, D0-7, AD0-3
+ ps.mi2c("", ('W', 26), 0, 0, 2)
+ ps.vss("I", ('W', 28), 0, 1, 1)
+ ps.vdd("I", ('W', 29), 0, 1, 1)
+ ps.vss("E", ('W', 30), 0, 1, 1)
+ ps.vdd("E", ('W', 31), 0, 1, 1)
- ps.vdd("E", ('W', 0), 0, 2, 1)
- ps.vss("E", ('W', 1), 0, 2, 1)
- ps.vdd("I", ('W', 2), 0, 2, 1)
- ps.vss("I", ('W', 3), 0, 2, 1)
- ps.sdram2("", ('W', 4), 0, 0, 12)
- ps.sdram1("", ('W', 16), 0, 21, 9)
- ps.uart("0", ('W', 22), 0)
- ps.jtag("", ('W', 24), 0, 0, 4)
- ps.vss("I", ('W', 28), 0, 3, 1)
- ps.vdd("I", ('W', 29), 0, 3, 1)
- ps.vss("E", ('W', 30), 0, 3, 1)
- ps.vdd("E", ('W', 31), 0, 3, 1)
+ ps.sdram2("", ('S', 0), 0, 0, 4) # 1st 4, AD10-12,DQM1
+ ps.vdd("E", ('S', 4), 0, 2, 1)
+ ps.vss("E", ('S', 5), 0, 2, 1)
+ ps.vdd("I", ('S', 6), 0, 2, 1)
+ ps.vss("I", ('S', 7), 0, 2, 1)
+ ps.sdram2("", ('S', 8), 0, 4, 8) # D8-15
+ ps.sdram1("", ('S', 16), 0, 21, 9) # clk etc.
+ ps.vss("I", ('S', 22), 0, 3, 1)
+ ps.vdd("I", ('S', 23), 0, 3, 1)
+ ps.vss("E", ('S', 24), 0, 3, 1)
+ ps.vdd("E", ('S', 25), 0, 3, 1)
+ ps.uart("0", ('S', 26), 0)
+ ps.mspi("0", ('S', 28), 0)
- ps.vss("I", ('E', 0), 0, 4, 1)
- ps.vdd("I", ('E', 1), 0, 4, 1)
- ps.vdd("I", ('E', 2), 0, 4, 1)
- ps.vss("I", ('E', 3), 0, 4, 1)
- ps.mspi("0", ('E', 4), 0)
- ps.gpio("", ('E', 9), 0, 0, 16)
- ps.eint("", ('E', 25), 0, 0, 3)
- ps.vss("I", ('E', 28), 0, 5, 1)
- ps.vdd("I", ('E', 29), 0, 5, 1)
- ps.vss("I", ('E', 30), 0, 5, 1)
- ps.vdd("I", ('E', 31), 0, 5, 1)
+ ps.gpio("", ('E', 0), 0, 0, 6) # GPIO 0-5
+ ps.vss("E", ('E', 6), 0, 4, 1)
+ ps.vdd("E", ('E', 7), 0, 4, 1)
+ ps.vdd("I", ('E', 8), 0, 4, 1)
+ ps.vss("I", ('E', 9), 0, 4, 1)
+ ps.gpio("", ('E', 10), 0, 6, 3) # GPIO 6-8
+ ps.jtag("", ('E', 13), 0, 0, 4)
+ ps.gpio("", ('E', 17), 0, 9, 5) # GPIO 9-13
+ ps.vss("I", ('E', 22), 0, 5, 1)
+ ps.vdd("I", ('E', 23), 0, 5, 1)
+ ps.vss("E", ('E', 24), 0, 5, 1)
+ ps.vdd("E", ('E', 25), 0, 5, 1)
+ ps.gpio("", ('E', 26), 0, 14, 2) # GPIO 14-15
+ ps.eint("", ('E', 28), 0, 0, 3)
+ ps.sys("", ('E', 31), 0, 5, 1) # analog VCO out in right top
- ps.vss("E", ('N', 0), 0, 6, 1)
- ps.vdd("E", ('N', 1), 0, 6, 1)
- ps.vdd("I", ('N', 2), 0, 6, 1)
- ps.vss("I", ('N', 3), 0, 6, 1)
+ ps.vss("E", ('N', 6), 0, 6, 1)
+ ps.vdd("E", ('N', 7), 0, 6, 1)
+ ps.vdd("I", ('N', 8), 0, 6, 1)
+ ps.vss("I", ('N', 9), 0, 6, 1)
#ps.pwm("", ('N', 2), 0, 0, 2) comment out (litex problem 25mar2021)
#ps.mspi("1", ('N', 7), 0) comment out (litex problem 25mar2021)
#ps.sdmmc("0", ('N', 11), 0) # comment out (litex problem 25mar2021)
- ps.sys("", ('N', 22), 0, 0, 6) # should be 6, to do all PLL pins
- ps.vss("I", ('N', 28), 0, 7, 1)
- ps.vdd("I", ('N', 29), 0, 7, 1)
- ps.vss("I", ('N', 30), 0, 7, 1)
- ps.vdd("I", ('N', 31), 0, 7, 1)
+ ps.sys("", ('N', 27), 0, 0, 5) # all but analog out in top right
+ ps.vss("I", ('N', 22), 0, 7, 1)
+ ps.vdd("I", ('N', 23), 0, 7, 1)
+ ps.vss("E", ('N', 24), 0, 7, 1)
+ ps.vdd("E", ('N', 25), 0, 7, 1)
#ps.mquadspi("1", ('S', 0), 0)
- print "ps clocks", ps.clocks
+ print ("ps clocks", ps.clocks)
# Scenarios below can be spec'd out as either "find first interface"
# by name/number e.g. SPI1, or as "find in bank/mux" which must be
pinmap = {}
litexmap = {}
- print p.muxed_cells
- print p.muxed_cells_bank
+ print (p.muxed_cells)
+ print (p.muxed_cells_bank)
ps = [''] * 32
pn = [''] * 32
padnum = int(padnum)
start = p.bankstart[bank]
banknum = padnum - start
- print "bank", bank, banknum, "padname", name, padnum, x
+ print ("bank", bank, banknum, "padname", name, padnum, x)
padbank = pads[bank]
pad = None
# VSS
#name = 'p_sys_rst_1'
pad = [name, name, name]
padbank[banknum] = name
- print "sys_rst add", bank, banknum, name
+ print ("sys_rst add", bank, banknum, name)
name = None
elif name == 'sys_pllclk':
name = None # ignore
pad = [name, name2, name2]
#if name:
# iopads.append([pname, name, name])
- print "sys pad", name
+ print ("sys pad", name)
# SPI Card
elif name.startswith('mspi0') or name.startswith('mspi1'):
domain = 'MSPI'
fn, name = orig_name.split("_")
if domain == 'PWM':
name = fn[3:]
- print psp.byspec
+ print (psp.byspec)
spec = None
for k in psp.byspec.keys():
if k.startswith(domain):
spec = psp.byspec[k]
- print "spec found", domain, spec
+ print ("spec found", domain, spec)
assert spec is not None
found = None
for pname in spec:
if pname.lower().startswith(name):
found = pname
- print "found spec", found
+ print ("found spec", found)
assert found is not None
# whewwww. add the direction onto the pad spec list
dirn = found[-1]
iopads.append([name, name2, name2, "-"])
nc_idx += 1
- print p.bankstart
+ print (p.bankstart)
pprint(psp.clocks)
- print
- print "N pads", pn
- print "S pads", ps
- print "E pads", pe
- print "W pads", pw
+ print()
+ print ("N pads", pn)
+ print ("S pads", ps)
+ print ("E pads", pe)
+ print ("W pads", pw)
# do not want these
del clocks['SYS']
del domains['SYS']
- print "chip domains (excluding sys-default)"
+ print ("chip domains (excluding sys-default)")
pprint(domains)
- print "chip clocks (excluding sys-default)"
+ print ("chip clocks (excluding sys-default)")
pprint(clocks)
- print "pin spec"
+ print ("pin spec")
pprint(psp.byspec)
chip = {
projects / pinmux.git / blobdiff