ps = PinSpec(pinbanks, fixedpins, function_names)
- ps.vss("E", ('N', 0), 0, 0, 1)
- ps.vdd("E", ('N', 1), 0, 0, 1)
- ps.sdram1("", ('N', 2), 0, 0, 30)
- ps.vss("I", ('N', 30), 0, 0, 1)
- ps.vdd("I", ('N', 31), 0, 0, 1)
+ ps.vdd("E", ('W', 0), 0, 0, 1)
+ ps.vss("E", ('W', 1), 0, 0, 1)
+ ps.vdd("I", ('W', 2), 0, 0, 1)
+ ps.vss("I", ('W', 3), 0, 0, 1)
+ ps.mi2c("", ('W', 4), 0, 0, 2)
+ ps.sdram1("", ('W', 6), 0, 0, 15) # SDRAM DAM0, D0-7, AD0-3
+ ps.vss("I", ('W', 22), 0, 1, 1)
+ ps.vdd("I", ('W', 23), 0, 1, 1)
+ ps.vss("E", ('W', 24), 0, 1, 1)
+ ps.vdd("E", ('W', 25), 0, 1, 1)
+ ps.sdram1("", ('W', 26), 0, 15, 6) # AD4-9
- ps.vss("E", ('E', 0), 0, 1, 1)
- ps.vdd("E", ('E', 1), 0, 1, 1)
- ps.sdram2("", ('E', 2), 0, 0, 12)
- ps.vss("I", ('E', 14), 0, 1, 1)
- ps.vdd("I", ('E', 15), 0, 1, 1)
- ps.gpio("", ('E', 16), 0, 8, 8)
- ps.jtag("", ('E', 25), 0, 0, 4)
+ ps.sdram2("", ('S', 0), 0, 0, 4) # 1st 4, AD10-12,DQM1
+ ps.vdd("E", ('S', 4), 0, 2, 1)
+ ps.vss("E", ('S', 5), 0, 2, 1)
+ ps.vdd("I", ('S', 6), 0, 2, 1)
+ ps.vss("I", ('S', 7), 0, 2, 1)
+ ps.sdram2("", ('S', 8), 0, 4, 8) # D8-15
+ ps.sdram1("", ('S', 16), 0, 21, 9) # clk etc.
+ ps.vss("I", ('S', 22), 0, 3, 1)
+ ps.vdd("I", ('S', 23), 0, 3, 1)
+ ps.vss("E", ('S', 24), 0, 3, 1)
+ ps.vdd("E", ('S', 25), 0, 3, 1)
+ ps.uart("0", ('S', 26), 0)
+ ps.mspi("0", ('S', 28), 0)
- ps.vss("I", ('S', 0), 0, 2, 1)
- ps.vdd("I", ('S', 1), 0, 2, 1)
- ps.mi2c("", ('S', 2), 0, 0, 2)
- ps.mspi("0", ('S', 8), 0)
- ps.uart("0", ('S', 13), 0)
- ps.gpio("", ('S', 15), 0, 0, 8)
- ps.sys("", ('S', 23), 0, 0, 7) # should be 7, to do all PLL pins
- ps.vss("I", ('S', 30), 0, 3, 1)
- ps.vdd("I", ('S', 31), 0, 3, 1)
+ ps.sys("", ('E', 0), 0, 5, 1) # analog VCO out in right top
+ ps.gpio("", ('E', 1), 0, 0, 5) # GPIO 0-4
+ ps.vss("E", ('E', 6), 0, 4, 1)
+ ps.vdd("E", ('E', 7), 0, 4, 1)
+ ps.vdd("I", ('E', 8), 0, 4, 1)
+ ps.vss("I", ('E', 9), 0, 4, 1)
+ ps.gpio("", ('E', 10), 0, 5, 3) # GPIO 5-7
+ ps.jtag("", ('E', 13), 0, 0, 4)
+ ps.gpio("", ('E', 17), 0, 8, 5) # GPIO 8-12
+ ps.vss("I", ('E', 22), 0, 5, 1)
+ ps.vdd("I", ('E', 23), 0, 5, 1)
+ ps.vss("E", ('E', 24), 0, 5, 1)
+ ps.vdd("E", ('E', 25), 0, 5, 1)
+ ps.gpio("", ('E', 26), 0, 13, 3) # GPIO 13-15
+ ps.eint("", ('E', 29), 0, 0, 3)
- ps.vss("E", ('W', 0), 0, 2, 1)
- ps.vdd("E", ('W', 1), 0, 2, 1)
- #ps.pwm("", ('W', 2), 0, 0, 2) comment out (litex problem 25mar2021)
- ps.eint("", ('W', 4), 0, 0, 3)
- #ps.mspi("1", ('W', 7), 0) comment out (litex problem 25mar2021)
- #ps.sdmmc("0", ('W', 11), 0) # comment out (litex problem 25mar2021)
- ps.vss("I", ('W', 30), 0, 4, 1)
- ps.vdd("I", ('W', 31), 0, 4, 1)
+ ps.vss("E", ('N', 6), 0, 6, 1)
+ ps.vdd("E", ('N', 7), 0, 6, 1)
+ ps.vdd("I", ('N', 8), 0, 6, 1)
+ ps.vss("I", ('N', 9), 0, 6, 1)
+ #ps.pwm("", ('N', 2), 0, 0, 2) comment out (litex problem 25mar2021)
+ #ps.mspi("1", ('N', 7), 0) comment out (litex problem 25mar2021)
+ #ps.sdmmc("0", ('N', 11), 0) # comment out (litex problem 25mar2021)
+ ps.sys("", ('N', 27), 0, 0, 5) # all but analog out in top right
+ ps.vss("I", ('N', 22), 0, 7, 1)
+ ps.vdd("I", ('N', 23), 0, 7, 1)
+ ps.vss("E", ('N', 24), 0, 7, 1)
+ ps.vdd("E", ('N', 25), 0, 7, 1)
#ps.mquadspi("1", ('S', 0), 0)
# SYS
elif name.startswith('sys'):
domain = 'SYS'
- if name == 'sys_clk':
+ if name == 'sys_pllclk':
pad = ["p_"+name, name, name]
elif name == 'sys_rst':
#name = 'p_sys_rst_1'
name = None # ignore
elif name == 'sys_pllvcout':
name = 'sys_pll_vco_o'
- pad = ['p_' + name, name, name]
+ pad = ['p_' + name, name, name, "A"] # A for Analog
elif name == 'sys_plltestout':
name = 'sys_pll_testout_o'
pad = ['p_' + name, name, name]
print "found spec", found
assert found is not None
# whewwww. add the direction onto the pad spec list
- pad.append(found[-1])
+ dirn = found[-1]
+ if pad[-1] == 'A':
+ pad[-1] += dirn
+ else:
+ pad.append(dirn)
iopads.append(pad)
elif pad is not None:
iopads.append(pad)