mirror W pins to match coriolis2 pad positions

[pinmux.git] / src / spec / ls180.py

diff --git a/src/spec/ls180.py b/src/spec/ls180.py
index c1b004bcfc945eeebb7ba2f8832743e429e5dae8..b7b8e46850547e18edadf5151b231f698be8c619 100644 (file)
--- a/src/spec/ls180.py
+++ b/src/spec/ls180.py
@@ -59,38 +59,60 @@ def pinspec():
 
     ps = PinSpec(pinbanks, fixedpins, function_names)
 
-    ps.vss("E", ('N', 0), 0, 0, 1)
-    ps.vdd("E", ('N', 1), 0, 0, 1)
-    ps.sdram1("", ('N', 2), 0, 0, 30)
-    ps.vss("I", ('N', 30), 0, 0, 1)
-    ps.vdd("I", ('N', 31), 0, 0, 1)
+    ps.sdram1("", ('W', 0), 0, 15, 6, rev=True) # AD4-9, turned round
+    ps.vdd("E", ('W', 6), 0, 0, 1)
+    ps.vss("E", ('W', 7), 0, 0, 1)
+    ps.vdd("I", ('W', 8), 0, 0, 1)
+    ps.vss("I", ('W', 9), 0, 0, 1)
+    ps.mi2c("", ('W', 10), 0, 0, 2)
+    ps.sdram1("", ('W', 12), 0, 0, 15) # SDRAM DAM0, D0-7, AD0-3
+    ps.vss("I", ('W', 28), 0, 1, 1)
+    ps.vdd("I", ('W', 29), 0, 1, 1)
+    ps.vss("E", ('W', 30), 0, 1, 1)
+    ps.vdd("E", ('W', 31), 0, 1, 1)
 
-    ps.vss("E", ('E', 0), 0, 1, 1)
-    ps.vdd("E", ('E', 1), 0, 1, 1)
-    ps.sdram2("", ('E', 2), 0, 0, 12)
-    ps.vss("I", ('E', 14), 0, 1, 1)
-    ps.vdd("I", ('E', 15), 0, 1, 1)
-    ps.gpio("", ('E', 16), 0, 8, 8)
-    ps.jtag("", ('E', 25), 0, 0, 4)
+    ps.sdram2("", ('S', 0), 0, 0, 4) # 1st 4, AD10-12,DQM1
+    ps.vdd("E", ('S', 4), 0, 2, 1)
+    ps.vss("E", ('S', 5), 0, 2, 1)
+    ps.vdd("I", ('S', 6), 0, 2, 1)
+    ps.vss("I", ('S', 7), 0, 2, 1)
+    ps.sdram2("", ('S', 8), 0, 4, 8) # D8-15
+    ps.sdram1("", ('S', 16), 0, 21, 9) # clk etc.
+    ps.vss("I", ('S', 22), 0, 3, 1)
+    ps.vdd("I", ('S', 23), 0, 3, 1)
+    ps.vss("E", ('S', 24), 0, 3, 1)
+    ps.vdd("E", ('S', 25), 0, 3, 1)
+    ps.uart("0", ('S', 26), 0)
+    ps.mspi("0", ('S', 28), 0)
 
-    ps.vss("I", ('S', 0), 0, 2, 1)
-    ps.vdd("I", ('S', 1), 0, 2, 1)
-    ps.mi2c("", ('S', 2), 0, 0, 2)
-    ps.mspi("0", ('S', 8), 0)
-    ps.uart("0", ('S', 13), 0)
-    ps.gpio("", ('S', 15), 0, 0, 8)
-    ps.sys("", ('S', 23), 0, 0, 2) # should be 7, to do all PLL pins
-    ps.vss("I", ('S', 30), 0, 3, 1)
-    ps.vdd("I", ('S', 31), 0, 3, 1)
+    ps.gpio("", ('E', 0), 0, 0, 6) # GPIO 0-5
+    ps.vss("E", ('E', 6), 0, 4, 1)
+    ps.vdd("E", ('E', 7), 0, 4, 1)
+    ps.vdd("I", ('E', 8), 0, 4, 1)
+    ps.vss("I", ('E', 9), 0, 4, 1)
+    ps.gpio("", ('E', 10), 0, 6, 3) # GPIO 6-8
+    ps.jtag("", ('E', 13), 0, 0, 4)
+    ps.gpio("", ('E', 17), 0, 9, 5) # GPIO 9-13
+    ps.vss("I", ('E', 22), 0, 5, 1)
+    ps.vdd("I", ('E', 23), 0, 5, 1)
+    ps.vss("E", ('E', 24), 0, 5, 1)
+    ps.vdd("E", ('E', 25), 0, 5, 1)
+    ps.gpio("", ('E', 26), 0, 14, 2) # GPIO 14-15
+    ps.eint("", ('E', 28), 0, 0, 3)
+    ps.sys("", ('E', 31), 0, 5, 1) # analog VCO out in right top
 
-    ps.vss("E", ('W', 0), 0, 2, 1)
-    ps.vdd("E", ('W', 1), 0, 2, 1)
-    #ps.pwm("", ('W', 2), 0, 0, 2)  comment out (litex problem 25mar2021)
-    ps.eint("", ('W', 4), 0, 0, 3)
-    #ps.mspi("1", ('W', 7), 0)       comment out (litex problem 25mar2021)
-    #ps.sdmmc("0", ('W', 11), 0)     # comment out (litex problem 25mar2021)
-    ps.vss("I", ('W', 30), 0, 4, 1)
-    ps.vdd("I", ('W', 31), 0, 4, 1)
+    ps.vss("E", ('N', 6), 0, 6, 1)
+    ps.vdd("E", ('N', 7), 0, 6, 1)
+    ps.vdd("I", ('N', 8), 0, 6, 1)
+    ps.vss("I", ('N', 9), 0, 6, 1)
+    #ps.pwm("", ('N', 2), 0, 0, 2)  comment out (litex problem 25mar2021)
+    #ps.mspi("1", ('N', 7), 0)       comment out (litex problem 25mar2021)
+    #ps.sdmmc("0", ('N', 11), 0)     # comment out (litex problem 25mar2021)
+    ps.sys("", ('N', 27), 0, 0, 5) # all but analog out in top right
+    ps.vss("I", ('N', 22), 0, 7, 1)
+    ps.vdd("I", ('N', 23), 0, 7, 1)
+    ps.vss("E", ('N', 24), 0, 7, 1)
+    ps.vdd("E", ('N', 25), 0, 7, 1)
 
     #ps.mquadspi("1", ('S', 0), 0)
 
@@ -190,7 +212,7 @@ def pinparse(psp, pinspec):
         # SYS
         elif name.startswith('sys'):
             domain = 'SYS'
-            if name == 'sys_clk':
+            if name == 'sys_pllclk':
                 pad = ["p_"+name, name, name]
             elif name == 'sys_rst':
                 #name = 'p_sys_rst_1'
@@ -202,7 +224,7 @@ def pinparse(psp, pinspec):
                 name = None # ignore
             elif name == 'sys_pllvcout':
                 name = 'sys_pll_vco_o'
-                pad = ['p_' + name, name, name]
+                pad = ['p_' + name, name, name, "A"] # A for Analog
             elif name == 'sys_plltestout':
                 name = 'sys_pll_testout_o'
                 pad = ['p_' + name, name, name]
@@ -299,7 +321,9 @@ def pinparse(psp, pinspec):
         # I2C master-only
         elif name.startswith('mtwi'):
             domain = 'MTWI'
-            name = 'i2c' + name[4:]
+            suffix = name[4:]
+            litex_name = 'mtwi' + suffix
+            name = 'i2c' + suffix
             if name.startswith('i2c_sda'):
                 name2 = 'i2c_sda_%s'
                 pad = ['p_'+name, name, name2 % 'o', name2 % 'i', name2 % 'oe']
@@ -378,7 +402,11 @@ def pinparse(psp, pinspec):
             print "found spec", found
             assert found is not None
             # whewwww.  add the direction onto the pad spec list
-            pad.append(found[-1])
+            dirn = found[-1]
+            if pad[-1] == 'A':
+                pad[-1] += dirn
+            else:
+                pad.append(dirn)
             iopads.append(pad)
         elif pad is not None:
             iopads.append(pad)