ps.mspi("0", ('S', 8), 0)
ps.uart("0", ('S', 13), 0)
ps.gpio("", ('S', 15), 0, 0, 8)
- ps.sys("", ('S', 23), 0, 0, 7)
+ ps.sys("", ('S', 23), 0, 0, 7) # should be 7, to do all PLL pins
ps.vss("I", ('S', 30), 0, 3, 1)
ps.vdd("I", ('S', 31), 0, 3, 1)
ps.vss("E", ('W', 0), 0, 2, 1)
ps.vdd("E", ('W', 1), 0, 2, 1)
- ps.pwm("", ('W', 2), 0, 0, 2)
+ #ps.pwm("", ('W', 2), 0, 0, 2) comment out (litex problem 25mar2021)
ps.eint("", ('W', 4), 0, 0, 3)
- ps.mspi("1", ('W', 7), 0)
- ps.sdmmc("0", ('W', 11), 0)
+ #ps.mspi("1", ('W', 7), 0) comment out (litex problem 25mar2021)
+ #ps.sdmmc("0", ('W', 11), 0) # comment out (litex problem 25mar2021)
ps.vss("I", ('W', 30), 0, 4, 1)
ps.vdd("I", ('W', 31), 0, 4, 1)
- #ps.mspi("0", ('W', 8), 0)
- #ps.mspi("1", ('W', 8), 0)
#ps.mquadspi("1", ('S', 0), 0)
# using "BM:Name". Pins are removed in-order as listed from
# lists (interfaces, EINTs, PWMs) from available pins.
- ls180 = ['SD0', 'UART0', 'GPIOS', 'GPIOE', 'JTAG', 'PWM', 'EINT',
+ ls180 = [
+ # 'SD0', litex problem 25mar2021
+ 'UART0', 'GPIOS', 'GPIOE', 'JTAG', 'PWM', 'EINT',
'VDD', 'VSS', 'SYS',
- 'MTWI', 'MSPI0', 'MSPI1', 'SDR']
+ 'MTWI', 'MSPI0',
+ # 'MSPI1', litex problem 25mar2021
+ 'SDR']
ls180_eint = []
ls180_pwm = []#['B0:PWM_0']
descriptions = {
def pinparse(psp, pinspec):
p = Parse(pinspec, verify=False)
pinmap = {}
+ litexmap = {}
print p.muxed_cells
print p.muxed_cells_bank
n_extpower = 0
for (padnum, name, x), bank in zip(p.muxed_cells, p.muxed_cells_bank):
orig_name = name
+ litex_name = None
domain = None # TODO, get this from the PinSpec. sigh
padnum = int(padnum)
start = p.bankstart[bank]
if name.startswith('vss'):
name = 'p_%s_' % name[:-2] + name[-1]
if 'i' in name:
- name = 'power_' + name[-1]
+ name = 'ground_' + name[-1]
name2 = 'vss'
else:
- name = 'iopower_' + name[-1]
+ name = 'ioground_' + name[-1]
name2 = 'iovss'
pad = [name, name2]
# VDD
elif name.startswith('vdd'):
if 'i' in name:
n_intpower += 1
- name = 'ground_' + name[-1]
+ name = 'power_' + name[-1]
name2 = 'vdd'
else:
n_extpower += 1
- name = 'ioground_' + name[-1]
+ name = 'iopower_' + name[-1]
name2 = 'iovdd'
pad = [name, name2]
# SYS
elif name.startswith('sys'):
domain = 'SYS'
if name == 'sys_clk':
- pad = [name, name, name]
+ pad = ["p_"+name, name, name]
elif name == 'sys_rst':
#name = 'p_sys_rst_1'
pad = [name, name, name]
name = None
elif name == 'sys_pllclk':
name = None # ignore
- elif name == 'sys_pllock':
- name = 'sys_pllock'
+ elif name == 'sys_pllvcout':
+ name = 'sys_pll_vco_o'
pad = ['p_' + name, name, name]
- elif name == 'sys_pllout':
- name = 'sys_pll_48_o'
+ elif name == 'sys_plltestout':
+ name = 'sys_pll_testout_o'
pad = ['p_' + name, name, name]
- elif name.startswith('sys_csel'):
+ elif name.startswith('sys_pllsel'):
i = name[-1]
name2 = 'sys_clksel_i(%s)' % i
name = 'p_sys_clksel_' + i
suffix = 'clk'
elif suffix == 'nss':
suffix = 'cs_n'
- if name.startswith('mspi1'):
+ if name.startswith('mspi0'):
prefix = 'spimaster_'
else:
prefix = 'spisdcard_'
+ litex_name = name[:6] + suffix
name = prefix + suffix
pad = ['p_' + name, name, name]
# SD/MMC
i = name[5:]
name = 'sdcard_data' + i
name2 = 'sdcard_data_%%s(%s)' % i
- pad = ['p_' + name, name, name2 % 'o', name2 % 'i',
- 'sdcard_data_oe']
+ pad = ['p_'+name, name, name2 % 'o', name2 % 'i', name2 % 'oe']
elif name.startswith('sd0_cmd'):
name = 'sdcard_cmd'
name2 = 'sdcard_cmd_%s'
else:
name = 'sdcard_' + name[4:]
pad = ['p_' + name, name, name]
+ litex_name = orig_name[:4] + "_".join(name.split("_")[1:])
# SDRAM
elif name.startswith('sdr'):
domain = 'SDR'
i = name[5:]
name = 'sdram_dq_' + i
name2 = 'sdram_dq_%%s(%s)' % i
- pad = ['p_'+name, name, name2 % 'o', name2 % 'i', 'sdram_dq_oe']
+ pad = ['p_'+name, name, name2 % 'o', name2 % 'i', name2 % 'oe']
elif name == 'sdr_csn0':
name = 'sdram_cs_n'
pad = ['p_' + name, name, name]
else:
name = 'sdram_' + name[4:]
pad = ['p_' + name, name, name]
+ litex_name = orig_name[:4] + "_".join(name.split("_")[1:])
# UART
elif name.startswith('uart'):
domain = 'UART'
pad = ['p_' + name, name, name]
# GPIO
elif name.startswith('gpio'):
+ gbank = name[4]
domain = 'GPIO'
i = name[7:]
name = 'gpio_' + i
name2 = 'gpio_%%s(%s)' % i
pad = ['p_' + name, name, name2 % 'o', name2 % 'i', name2 % 'oe']
print ("GPIO pad", name, pad)
+ litex_name = "gpio_%s" % gbank + "_".join(name.split("_")[1:])
# I2C master-only
elif name.startswith('mtwi'):
domain = 'MTWI'
- name = 'i2c' + name[4:]
+ suffix = name[4:]
+ litex_name = 'mtwi' + suffix
+ name = 'i2c' + suffix
if name.startswith('i2c_sda'):
name2 = 'i2c_sda_%s'
pad = ['p_'+name, name, name2 % 'o', name2 % 'i', name2 % 'oe']
domain = 'EINT'
i = name[-1]
name = 'eint_%s' % i
- name2 = 'eint(%s)' % i
+ name2 = 'eint_%s' % i
pad = ['p_' + name, name2, name2]
# PWM
elif name.startswith('pwm'):
pad = ['p_' + name, name, name]
print ("GPIO pad", name, pad)
+ if litex_name is None:
+ litex_name = name
+
# JTAG domain
if name and name.startswith('jtag'):
domain = 'JTAG'
clocks[domain] = name
# record remap
pinmap[orig_name] = name
+ litexmap[litex_name] = name
# add pad to iopads
if domain and pad is not None:
fn, name = orig_name.split("_")
if domain == 'PWM':
name = fn[3:]
- print dir(psp)
- print dir(p)
print psp.byspec
spec = None
for k in psp.byspec.keys():
'pads.instances' : iopads,
'pins.specs' : psp.byspec,
'pins.map' : pinmap,
+ 'litex.map' : litexmap,
'chip.domains' : domains,
'chip.clocks' : clocks,
'chip.n_intpower': n_intpower,
'chip.n_extpower': n_extpower,
}
- chip = json.dumps(chip)
- with open("ls180/litex_pinpads.json", "w") as f:
- f.write(chip)
-
- return pinmap
+ return pinmap, chip