Fixed gpio W number

[pinmux.git] / src / spec / ls2.py

diff --git a/src/spec/ls2.py b/src/spec/ls2.py
index 7a9380741d97a53c487b03ece73b3927244b46af..2fcbd709ae88f792cff5b92695a8e040511abefb 100644 (file)
--- a/src/spec/ls2.py
+++ b/src/spec/ls2.py
@@ -59,17 +59,20 @@ def pinspec():
 
     ps = PinSpec(pinbanks, fixedpins, function_names)
 
-    ps.sdram1("", ('W', 0), 0, 15, 6, rev=True) # AD4-9, turned round
+    ps.gpio("", ('W', 0), 0, 0, 6) # GPIO 0-5
+    ps.sdram1("", ('W', 0), 1, 15, 6, rev=True) # AD4-9, turned round
     ps.vdd("E", ('W', 6), 0, 0, 1)
     ps.vss("E", ('W', 7), 0, 0, 1)
     ps.vdd("I", ('W', 8), 0, 0, 1)
     ps.vss("I", ('W', 9), 0, 0, 1)
-    ps.sdram1("", ('W', 10), 0, 0, 15, rev=True) # SDRAM DAM0, D0-7, AD0-3
-    ps.mi2c("", ('W', 26), 0, 0, 2)
-    ps.vss("I", ('W', 28), 0, 1, 1)
-    ps.vdd("I", ('W', 29), 0, 1, 1)
-    ps.vss("E", ('W', 30), 0, 1, 1)
-    ps.vdd("E", ('W', 31), 0, 1, 1)
+    ps.gpio("", ('W', 10), 0, 6, 15) # GPIO 6-20
+    ps.sdram1("", ('W', 10), 1, 0, 15, rev=True) # SDRAM DAM0, D0-7, AD0-3
+    ps.vss("I", ('W', 25), 0, 1, 1)
+    ps.vdd("I", ('W', 26), 0, 1, 1)
+    ps.vss("E", ('W', 27), 0, 1, 1)
+    ps.vdd("E", ('W', 28), 0, 1, 1)
+    ps.gpio("", ('W', 29), 0, 21, 3) # GPIO 21-23
+    ps.mi2c("", ('W', 30), 1, 0, 2)
 
     ps.gpio("", ('S', 0), 0, 0, 4) # GPIO 0-4
     ps.sdram2("", ('S', 0), 1, 0, 4) # 1st 4, AD10-12,DQM1
@@ -101,7 +104,7 @@ def pinspec():
     ps.vdd("I", ('E', 23), 0, 5, 1)
     ps.vss("E", ('E', 24), 0, 5, 1)
     ps.vdd("E", ('E', 25), 0, 5, 1)
-    ps.gpio("", ('E', 26), 0, 14, 5) # GPIO 14-18
+    ps.gpio("", ('E', 26), 0, 16, 5) # GPIO 14-18
     ps.rgmii("1", ('E', 26), 1, 14, 5) # more RGMII-2
     ps.eint("", ('E', 28), 2, 0, 3)
     ps.sys("", ('E', 31), 0, 5, 1) # analog VCO out in right top
@@ -136,9 +139,10 @@ def pinspec():
 
     ls180 = [
             # 'SD0', litex problem 25mar2021
-            'UART0', 'GPIOS', 'GPIOE', 'JTAG', 'PWM', 'EINT',
+            'UART0', 'JTAG', 'PWM', 'EINT',
              'VDD', 'VSS', 'SYS',
                 'MTWI', 'MSPI0',
+                'RG0', 'RG1',
                 # 'MSPI1', litex problem 25mar2021
                 'SDR']
     ls180_eint = []
@@ -151,6 +155,8 @@ def pinspec():
         'MSPI1': '',
         'UART0': '',
         'LPC1': '',
+        'RG0': '',
+        'RG1': '',
         'SYS': '',
         'LPC2': '',
         'SDR': '',