rework spec generation functions

[pinmux.git] / src / spec / m_class.py

diff --git a/src/spec/m_class.py b/src/spec/m_class.py
index 8c176423b19b76a7c33842ebfb059ae4dca194eb..3f3974b8e65f7595faa1eb74aa1d11eeedf3a8ab 100644 (file)
--- a/src/spec/m_class.py
+++ b/src/spec/m_class.py
@@ -25,48 +25,48 @@ def pinspec():
     pinouts = Pinouts(bankspec)
 
     # Bank A, 0-15
-    pinouts.gpio("", ('A', 0), "A", 0, 16, 0)
+    pinouts.gpio("", ('A', 0), "A", 0, 0, 16)
     pinouts.spi("0", ('A', 0), "A", 3)
     pinouts.uartfull("1", ('A', 0), "A", 2)
     pinouts.i2c("0", ('A', 4), "A", 2)
     pinouts.emmc("", ('A', 0), "A", 1)
     #pinouts.uart("0", ('A', 14), "A", 1)
     pinouts.spi("1", ('A', 6), "A", 2)
-    pinouts.eint("", ('A', 10), "A", 0, 6)
-    pinouts.eint("", ('A', 4), "A", 0, 6, mux=3)
+    pinouts.eint("", ('A', 10), "A", 1, start=0, limit=6)
+    pinouts.eint("", ('A', 4), "A", 3, start=0, limit=6)
     pinouts.sdmmc("0", ('A', 10), "A", 2)
     pinouts.jtag("0", ('A', 10), "A", 3)
     pinouts.uart("0", ('A', 14), "A", 3)
 
     # Bank B, 16-47
-    pinouts.gpio("", ('B', 0), "B", 0, 28, 0)
+    pinouts.gpio("", ('B', 0), "B", 0, 0, 28)
     pinouts.rgbttl("0", ('B', 0), "B", 1)
     pinouts.spi("0", ('B', 12), "B", 2)
     pinouts.quadspi("", ('B', 4), "B", 2, limit=4)
     pinouts.uart("1", ('B', 16), "B", 2)
     pinouts.i2c("2", ('B', 18), "B", 2)
-    pinouts.pwm("", ('B', 9), "B", 0, 1, mux=2)
-    pinouts.pwm("", ('B', 20), "B", 1, 2, mux=2)
+    pinouts.pwm("", ('B', 9), "B", 2, start=0, limit=1)
+    pinouts.pwm("", ('B', 20), "B", 2, start=1, limit=2)
     pinouts.sdmmc("0", ('B', 22), "B", 2)
-    pinouts.eint("", ('B', 0), "B", 6, 4, mux=3)
+    pinouts.eint("", ('B', 0), "B", 3, start=6, limit=4)
     pinouts.flexbus2("", ('B', 4), "B", 3)
     pinouts.i2c("0", ('B', 0), "B", 2)
     pinouts.uart("0", ('B', 2), "B", 2)
     pinouts.uart("2", ('B', 10), "B", 2)
 
     # Bank C, 48-71
-    pinouts.gpio("", ("C", 0), "C", 0, 24, 0)
+    pinouts.gpio("", ("C", 0), "C", 0, 0, 24)
     pinouts.ulpi("0", ('C', 0), "C", 1)
     pinouts.ulpi("1", ('C', 12), "C", 1)
     pinouts.spi("1", ('C', 8), "C", 2)
     #pinouts.spi("1", ('C', 28), "C", 2)
     pinouts.uartfull("0", ('C', 20), "C", 3)
-    pinouts.eint("", ('C', 0), "C", 10, 8, mux=3)
+    pinouts.eint("", ('C', 0), "C", 3, start=10, limit=8)
     pinouts.jtag("1", ('C', 8), "C", 3)
-    pinouts.eint("", ('C', 12), "C", 22, 8, mux=3)
+    pinouts.eint("", ('C', 12), "C", 3, start=22, limit=8)
     pinouts.uart("0", ('C', 22), "C", 2)
     pinouts.i2s("", ('C', 13), "C", 2)
-    pinouts.pwm("", ('C', 21), "C", 2, 1, mux=2)
+    pinouts.pwm("", ('C', 21), "C", 2, start=2, limit=1)
 
     # Bank D, 72-96
 
@@ -91,49 +91,49 @@ def pinspec():
         'FB_TSIZ1': ('FB_BWE1', 2, "D"),
     }
     #pinouts.mcu8080("", 72, "D", 1)
-    pinouts.gpio("", ('D', 0), "D", 0, 24, 0)
+    pinouts.gpio("", ('D', 0), "D", 0, 0, 24)
     pinouts.flexbus1("", ('D', 0), "D", 1, spec=flexspec)
     pinouts.i2c("1", ('D', 8), "D", 3)
-    pinouts.pwm("", ('D', 21), "D", 0, 3, mux=1)
+    pinouts.pwm("", ('D', 21), "D", 1, start=0, limit=3)
     pinouts.i2c("0", ('D', 10), "D", 3)
     pinouts.i2c("2", ('D', 19), "D", 2)
     pinouts.uartfull("0", ('D', 0), "D", 2)
     pinouts.uart("1", ('D', 21), "D", 2)
     pinouts.uart("2", ('D', 13), "D", 2)
-    pinouts.eint("", ('D', 19), "D", 18, 4, mux=3)
-    pinouts.eint("", ('D', 23), "D", 9, 1, mux=3)
-    pinouts.eint("", ('D', 13), "D", 5, 4, mux=3)
-    pinouts.eint("", ('D', 0), "D", 30, 2, mux=3)
+    pinouts.eint("", ('D', 19), "D", 3, start=18, limit=4)
+    pinouts.eint("", ('D', 23), "D", 3, start=9, limit=1)
+    pinouts.eint("", ('D', 13), "D", 3, start=5, limit=4)
+    pinouts.eint("", ('D', 0), "D", 3, start=30, limit=2)
     pinouts.i2c("1", ('D', 2), "D", 3)
     pinouts.sdmmc("1", ('D', 4), "D", 2)
 
     # Bank E
-    pinouts.gpio("", ('E', 0), "E", 0, 24, 0)
+    pinouts.gpio("", ('E', 0), "E", 0, 0, 24)
     pinouts.flexbus2("", ('E', 0), "E", 1)
     pinouts.sdmmc("1", ('E', 0), "E", 2)
     pinouts.sdmmc("2", ('E', 8), "E", 2)
     pinouts.quadspi("", ('E', 18), "E", 2)
     pinouts.uartfull("1", ('E', 14), "E", 2)
     pinouts.i2c("1", ('E', 6), "E", 2)
-    pinouts.eint("", ('E', 0), "E", 10, 8, mux=3)
-    pinouts.eint("", ('E', 8), "E", 22, 6, mux=3)
+    pinouts.eint("", ('E', 0), "E", 3, start=10, limit=8)
+    pinouts.eint("", ('E', 8), "E", 3, start=22, limit=6)
     pinouts.emmc("", ('E', 14), "E", 3)
 
     # Bank F
-    pinouts.gpio("", ('F', 0), "F", 0, 10, 0)
+    pinouts.gpio("", ('F', 0), "F", 0, 0, 10)
     pinouts.i2s("", ('F', 0), "F", 1)
     pinouts.i2c("0", ('F', 6), "F", 2)
-    pinouts.pwm("", ('F', 8), "F", 0, 1, mux=2)
-    pinouts.pwm("", ('F', 9), "F", 1, 1, mux=2)
+    pinouts.pwm("", ('F', 8), "F", 2, start=0, limit=1)
+    pinouts.pwm("", ('F', 9), "F", 2, start=1, limit=1)
     pinouts.uart("2", ('F', 8), "F", 1)
     pinouts.sdmmc("2", ('F', 0), "F", 2)
-    pinouts.eint("", ('F', 0), "F", 18, 4, mux=3)
-    pinouts.pwm("", ('F', 4), "F", 2, 1, mux=3)
-    pinouts.eint("", ('F', 5), "F", 7, 1, mux=3)
-    pinouts.eint("", ('F', 6), "F", 28, 4, mux=3)
+    pinouts.eint("", ('F', 0), "F", 3, start=18, limit=4)
+    pinouts.pwm("", ('F', 4), "F", 3, start=2, limit=1)
+    pinouts.eint("", ('F', 5), "F", 3, start=7, limit=1)
+    pinouts.eint("", ('F', 6), "F", 3, start=28, limit=4)
 
     # Bank G
-    pinouts.gpio("", ('G', 0), "G", 0, 32, 0)
+    pinouts.gpio("", ('G', 0), "G", 0, 0, 32)
     pinouts.rgmii("", ('G', 0), "G", 1)
     pinouts.ulpi("2", ('G', 20), "G", 1)
     pinouts.rgbttl("1", ('G', 0), "G", 2)