'GPIO': 'GPIO',
'EINT': 'External Interrupt',
'PWM': 'PWM',
+ 'RG0': 'Gigabit Ethernet 0',
+ 'RG1': 'Gigabit Ethernet 1',
'JTAG': 'JTAG',
'MTWI': 'I2C Master 1',
'SD0': 'SD/MMC 1',
ps.vdd("E", ('E', 25), 0, 5, 1)
ps.gpio("", ('E', 26), 0, 14, 2) # GPIO 14-15
ps.eint("", ('E', 28), 0, 0, 3)
- ps.sys("", ('E', 31), 0, 5, 1) # analog VCO out in right top
+ ps.rgmii("0", ('E', 31), 0, 0, 18)
+ ps.sys("", ('E', 63), 0, 5, 1) # analog VCO out in right top
ps.vss("E", ('N', 6), 0, 6, 1)
ps.vdd("E", ('N', 7), 0, 6, 1)
ps.vdd("I", ('N', 8), 0, 6, 1)
ps.vss("I", ('N', 9), 0, 6, 1)
+ ps.rgmii("1", ('N', 10), 0, 0, 18)
#ps.pwm("", ('N', 2), 0, 0, 2) comment out (litex problem 25mar2021)
#ps.mspi("1", ('N', 7), 0) comment out (litex problem 25mar2021)
#ps.sdmmc("0", ('N', 11), 0) # comment out (litex problem 25mar2021)
- ps.sys("", ('N', 27), 0, 0, 5) # all but analog out in top right
- ps.vss("I", ('N', 22), 0, 7, 1)
- ps.vdd("I", ('N', 23), 0, 7, 1)
- ps.vss("E", ('N', 24), 0, 7, 1)
- ps.vdd("E", ('N', 25), 0, 7, 1)
+ ps.sys("", ('N', 59), 0, 0, 5) # all but analog out in top right
+ ps.vss("I", ('N', 54), 0, 7, 1)
+ ps.vdd("I", ('N', 55), 0, 7, 1)
+ ps.vss("E", ('N', 56), 0, 7, 1)
+ ps.vdd("E", ('N', 57), 0, 7, 1)
#ps.mquadspi("1", ('S', 0), 0)
- print "ps clocks", ps.clocks
+ print ("ps clocks", ps.clocks)
# Scenarios below can be spec'd out as either "find first interface"
# by name/number e.g. SPI1, or as "find in bank/mux" which must be
'UART0', 'GPIOS', 'GPIOE', 'JTAG', 'PWM', 'EINT',
'VDD', 'VSS', 'SYS',
'MTWI', 'MSPI0',
+ 'RG0', 'RG1',
# 'MSPI1', litex problem 25mar2021
'SDR']
ngi_router_eint = []
pinmap = {}
litexmap = {}
- print p.muxed_cells
- print p.muxed_cells_bank
+ print (p.muxed_cells)
+ print (p.muxed_cells_bank)
# TODO - Turn the number of pins per side into a variable?
ps = [''] * 64
padnum = int(padnum)
start = p.bankstart[bank]
banknum = padnum - start
- print "bank", bank, banknum, "padname", name, padnum, x
+ print ("bank", bank, banknum, "padname", name, padnum, x)
padbank = pads[bank]
pad = None
# VSS
#name = 'p_sys_rst_1'
pad = [name, name, name]
padbank[banknum] = name
- print "sys_rst add", bank, banknum, name
+ print ("sys_rst add", bank, banknum, name)
name = None
elif name == 'sys_pllclk':
name = None # ignore
pad = [name, name2, name2]
#if name:
# iopads.append([pname, name, name])
- print "sys pad", name
+ print ("sys pad", name)
# SPI Card
elif name.startswith('mspi0') or name.startswith('mspi1'):
domain = 'MSPI'
fn, name = orig_name.split("_")
if domain == 'PWM':
name = fn[3:]
- print psp.byspec
+ print (psp.byspec)
spec = None
for k in psp.byspec.keys():
if k.startswith(domain):
spec = psp.byspec[k]
- print "spec found", domain, spec
+ print ("spec found", domain, spec)
assert spec is not None
found = None
for pname in spec:
if pname.lower().startswith(name):
found = pname
- print "found spec", found
+ print ("found spec", found)
assert found is not None
# whewwww. add the direction onto the pad spec list
dirn = found[-1]
iopads.append([name, name2, name2, "-"])
nc_idx += 1
- print p.bankstart
+ print (p.bankstart)
pprint(psp.clocks)
print
- print "N pads", pn
- print "S pads", ps
- print "E pads", pe
- print "W pads", pw
+ print ("N pads", pn)
+ print ("S pads", ps)
+ print ("E pads", pe)
+ print ("W pads", pw)
# do not want these
del clocks['SYS']
del domains['SYS']
- print "chip domains (excluding sys-default)"
+ print ("chip domains (excluding sys-default)")
pprint(domains)
- print "chip clocks (excluding sys-default)"
+ print ("chip clocks (excluding sys-default)")
pprint(clocks)
- print "pin spec"
+ print ("pin spec")
pprint(psp.byspec)
chip = {