fixed list bracket typo

[pinmux.git] / src / spec / pinfunctions.py

diff --git a/src/spec/pinfunctions.py b/src/spec/pinfunctions.py
index 451e652a42b10627f3746d64354ac3396d37cd12..68e62ea56f1cf6afa0bc54d412c6fb5181732503 100644 (file)
--- a/src/spec/pinfunctions.py
+++ b/src/spec/pinfunctions.py
@@ -48,13 +48,13 @@
 
 def i2s(suffix, bank):
     return (['MCK+', 'BCK+', 'LRCK+', 'DI-', 'DO+'],
-            [])
+            [], "MCK")
 
 
 # XXX TODO: correct these.  this is a stub for now
 # https://bugs.libre-soc.org/show_bug.cgi?id=303
 def lpc(suffix, bank, pincount=4):
-    lpcpins = ['CMD+', 'CLK+']
+    lpcpins = ['CMD*', 'CLK+']
     inout = []
     for i in range(pincount):
         pname = "D%d*" % i
@@ -64,7 +64,7 @@ def lpc(suffix, bank, pincount=4):
 
 
 def emmc(suffix, bank, pincount=8):
-    emmcpins = ['CMD+', 'CLK+']
+    emmcpins = ['CMD*', 'CLK+']
     inout = []
     for i in range(pincount):
         pname = "D%d*" % i
@@ -110,9 +110,17 @@ def quadspi(suffix, bank):
 
 
 def i2c(suffix, bank):
+    """bi-directional (reversible, master-slave) I2C
+    """
     return (['SDA*', 'SCL*'], [], 'SCL')
 
 
+def mi2c(suffix, bank):
+    """master-only I2C (clock is output only)
+    """
+    return (['SDA*', 'SCL+'], [], 'SCL')
+
+
 def jtag(suffix, bank):
     return (['TMS-', 'TDI-', 'TDO+', 'TCK+'], [], 'TCK')
 
@@ -143,12 +151,13 @@ def rgmii(suffix, bank):
     buspins = []
     for i in range(4):
         buspins.append("ERXD%d-" % i)
+    buspins += ['ERXCK-', 'ERXERR-']
     for i in range(4):
         buspins.append("ETXD%d+" % i)
-    buspins += ['ERXCK-', 'ERXERR-', 'ERXDV-',
+    buspins += ['ETXCK-', 'ETXERR-',
+                'ETXEN+', 'ERXDV-',
                 'EMDC+', 'EMDIO*',
-                'ETXEN+', 'ETXCK+', 'ECRS-',
-                'ECOL+', 'ETXERR+']
+                'ECRS-', 'ECOL+']
     return (buspins, [], ['ERXCK', 'ETXCK'])
 
 
@@ -189,10 +198,10 @@ def sdram1(suffix, bank, n_adr=10):
         pname = "D%d*" % i
         buspins.append(pname)
         inout.append(pname)
-    for i in range(n_adr):
-        buspins.append("AD%d+" % i)
     for i in range(2):
         buspins.append("BA%d+" % i)
+    for i in range(n_adr):
+        buspins.append("AD%d+" % i)
     buspins += ['CLK+', 'CKE+', 'RASn+', 'CASn+', 'WEn+',
                 'CSn0+']
     return (buspins, inout, 'CLK')
@@ -204,7 +213,7 @@ def sdram2(suffix, bank):
     for i in range(10, 13):
         buspins.append("AD%d+" % i)
     for i in range(1, 2):
-        pname = "DQM%d*" % i
+        pname = "DQM%d+" % i
         buspins.append(pname)
     for i in range(8, 16):
         pname = "D%d*" % i
@@ -221,7 +230,7 @@ def sdram3(suffix, bank):
     for i in range(13, 14):
         buspins.append("AD%d+" % i)
     for i in range(1, 4):
-        pname = "DQM%d*" % i
+        pname = "DQM%d+" % i
     for i in range(8, 32):
         pname = "D%d*" % i
         buspins.append(pname)
@@ -277,8 +286,12 @@ def vdd(suffix, bank):
     return (RangePin("-"), [], None)
 
 def sys(suffix, bank):
-    return (['CLK-', 'RST-', 'PLLCLK-', 'PLLOUT+',
-             'CSEL0-', 'CSEL1-', 'CSEL2-'], [], 'CLK')
+    return (['RST-',                       # reset line
+             'PLLCLK-',                       # incoming clock (to PLL)
+             'PLLSELA0-', 'PLLSELA1-',     # PLL divider-selector
+             'PLLTESTOUT+',                # divided-output (for testing)
+             'PLLVCOUT+',                  # PLL VCO analog out (for testing)
+             ], [], 'CLK')
 
 # list functions by name here
 
@@ -291,6 +304,7 @@ pinspec = (('IIS', i2s),
            ('SPI', spi),
            ('QSPI', quadspi),
            ('TWI', i2c),
+           ('MTWI', mi2c),
            ('JTAG', jtag),
            ('UART', uart),
            ('QUART', uartfull),