(['CMD+', 'CLK+', 'D0*', 'D1*', 'D2*', 'D3*'] # pin names
['D0*', 'D1*', 'D2*', 'D3*']) # ganged bus names
+
+ addition:
+
+ 3rd item in list gives the name of the clock.
"""
def i2s(suffix, bank):
return (['MCK+', 'BCK+', 'LRCK+', 'DI-', 'DO+'],
- [])
+ [], "MCK")
# XXX TODO: correct these. this is a stub for now
# https://bugs.libre-soc.org/show_bug.cgi?id=303
def lpc(suffix, bank, pincount=4):
- lpcpins = ['CMD+', 'CLK+']
+ lpcpins = ['CMD*', 'CLK+']
inout = []
for i in range(pincount):
pname = "D%d*" % i
lpcpins.append(pname)
inout.append(pname)
- return (lpcpins, inout)
+ return (lpcpins, inout, 'CLK')
def emmc(suffix, bank, pincount=8):
- emmcpins = ['CMD+', 'CLK+']
+ emmcpins = ['CMD*', 'CLK+']
inout = []
for i in range(pincount):
pname = "D%d*" % i
emmcpins.append(pname)
inout.append(pname)
- return (emmcpins, inout)
+ return (emmcpins, inout, 'CLK')
def sdmmc(suffix, bank):
pname = "IO%d*" % i
qpins.append(pname)
inout.append(pname)
- return (qpins, inout)
+ return (qpins, inout, 'CK')
def mspi(suffix, bank):
def i2c(suffix, bank):
- return (['SDA*', 'SCL*'], [])
+ """bi-directional (reversible, master-slave) I2C
+ """
+ return (['SDA*', 'SCL*'], [], 'SCL')
+
+
+def mi2c(suffix, bank):
+ """master-only I2C (clock is output only)
+ """
+ return (['SDA*', 'SCL+'], [], 'SCL')
def jtag(suffix, bank):
- return (['TMS-', 'TDI-', 'TDO+', 'TCK+'], [])
+ return (['TMS-', 'TDI-', 'TDO+', 'TCK+'], [], 'TCK')
def uart(suffix, bank):
- return (['TX+', 'RX-'], [])
+ return (['TX+', 'RX-'], [], None)
def ulpi(suffix, bank):
ulpipins = ['CK+', 'DIR+', 'STP+', 'NXT+']
for i in range(8):
ulpipins.append('D%d*' % i)
- return (ulpipins, [])
+ return (ulpipins, [], 'CK')
def uartfull(suffix, bank):
- return (['TX+', 'RX-', 'CTS-', 'RTS+'],
- [])
+ return (['TX+', 'RX-', 'CTS-', 'RTS+'], [], None)
def rgbttl(suffix, bank):
ttlpins = ['CK+', 'DE+', 'HS+', 'VS+']
for i in range(24):
ttlpins.append("OUT%d+" % i)
- return (ttlpins, [])
+ return (ttlpins, [], 'CK')
def rgmii(suffix, bank):
buspins = []
for i in range(4):
buspins.append("ERXD%d-" % i)
+ buspins += ['ERXCK-', 'ERXERR-']
for i in range(4):
buspins.append("ETXD%d+" % i)
- buspins += ['ERXCK-', 'ERXERR-', 'ERXDV-',
+ buspins += ['ETXCK-', 'ETXERR-',
+ 'ETXEN+', 'ERXDV-',
'EMDC+', 'EMDIO*',
- 'ETXEN+', 'ETXCK+', 'ECRS-',
- 'ECOL+', 'ETXERR+']
- return (buspins, [])
+ 'ECRS-', 'ECOL+']
+ return (buspins, [], ['ERXCK', 'ETXCK'])
def flexbus1(suffix, bank):
buspins.append("BWE%d+" % i)
for i in range(2, 6):
buspins.append("CS%d+" % i)
- return (buspins, inout)
+ return (buspins, inout, None)
def flexbus2(suffix, bank):
buspins = []
for i in range(8, 32):
buspins.append("AD%d*" % i)
- return (buspins, buspins)
+ return (buspins, buspins, None)
def sdram1(suffix, bank, n_adr=10):
pname = "D%d*" % i
buspins.append(pname)
inout.append(pname)
- for i in range(n_adr):
- buspins.append("AD%d+" % i)
for i in range(2):
buspins.append("BA%d+" % i)
+ for i in range(n_adr):
+ buspins.append("AD%d+" % i)
buspins += ['CLK+', 'CKE+', 'RASn+', 'CASn+', 'WEn+',
'CSn0+']
- return (buspins, inout)
+ return (buspins, inout, 'CLK')
def sdram2(suffix, bank):
buspins = []
inout = []
for i in range(10, 13):
- buspins.append("SDRAD%d+" % i)
+ buspins.append("AD%d+" % i)
for i in range(1, 2):
- pname = "DQM%d*" % i
+ pname = "DQM%d+" % i
buspins.append(pname)
for i in range(8, 16):
pname = "D%d*" % i
buspins.append(pname)
inout.append(pname)
- return (buspins, inout)
+ return (buspins, inout, None)
def sdram3(suffix, bank):
for i in range(1, 6):
buspins.append("CSn%d+" % i)
for i in range(13, 14):
- buspins.append("SDRAD%d+" % i)
+ buspins.append("AD%d+" % i)
for i in range(1, 4):
- pname = "DQM%d*" % i
+ pname = "DQM%d+" % i
for i in range(8, 32):
- pname = "SDRD%d*" % i
+ pname = "D%d*" % i
buspins.append(pname)
inout.append(pname)
- return (buspins, inout)
+ return (buspins, inout, None)
def mcu8080(suffix, bank):
buspins = []
inout = []
for i in range(8):
- pname = "MCUD%d*" % i
+ pname = "D%d*" % i
buspins.append(pname)
inout.append(pname)
for i in range(8):
- buspins.append("MCUAD%d+" % (i + 8))
+ buspins.append("AD%d+" % (i + 8))
for i in range(6):
- buspins.append("MCUCS%d+" % i)
+ buspins.append("CS%d+" % i)
for i in range(2):
- buspins.append("MCUNRB%d+" % i)
- buspins += ['MCUCD+', 'MCURD+', 'MCUWR+', 'MCUCLE+', 'MCUALE+',
- 'MCURST+']
- return (buspins, inout)
+ buspins.append("NRB%d+" % i)
+ buspins += ['CD+', 'RD+', 'WR+', 'CLE+', 'ALE+',
+ 'RST+']
+ return (buspins, inout, None)
class RangePin(object):
def eint(suffix, bank):
- return (RangePin("-"), [])
+ return (RangePin("-"), [], None)
def pwm(suffix, bank):
- return (RangePin("+"), [])
+ return (RangePin("+"), [], None)
def gpio(suffix, bank):
- return (("GPIO%s" % bank, RangePin(prefix=bank, suffix="*")), [])
+ return (("GPIO%s" % bank, RangePin(prefix=bank, suffix="*")), [], None)
def vss(suffix, bank):
- return (RangePin("-"), [])
+ return (RangePin("-"), [], None)
def vdd(suffix, bank):
- return (RangePin("-"), [])
-
-def clk(suffix, bank):
- return (RangePin("-"), [])
+ return (RangePin("-"), [], None)
-def rst(suffix, bank):
- return (RangePin("-"), [])
+def sys(suffix, bank):
+ return (['RST-', # reset line
+ 'PLLCLK-', # incoming clock (to PLL)
+ 'PLLSELA0-', 'PLLSELA1-', # PLL divider-selector
+ 'PLLTESTOUT+', # divided-output (for testing)
+ 'PLLVCOUT+', # PLL VCO analog out (for testing)
+ ], [], 'CLK')
# list functions by name here
pinspec = (('IIS', i2s),
('LPC', lpc),
('EMMC', emmc),
- ('MMC', sdmmc),
+ ('SD', sdmmc),
('MSPI', mspi),
('MQSPI', mquadspi),
('SPI', spi),
('QSPI', quadspi),
('TWI', i2c),
+ ('MTWI', mi2c),
('JTAG', jtag),
('UART', uart),
('QUART', uartfull),
('SDR', sdram3),
('VSS', vss),
('VDD', vdd),
- ('CLK', clk),
- ('RST', rst),
+ ('SYS', sys),
('EINT', eint),
('PWM', pwm),
('GPIO', gpio),
projects / pinmux.git / blobdiff