pname = "D%d*" % i
buspins.append(pname)
inout.append(pname)
- for i in range(n_adr):
- buspins.append("AD%d+" % i)
for i in range(2):
buspins.append("BA%d+" % i)
+ for i in range(n_adr):
+ buspins.append("AD%d+" % i)
buspins += ['CLK+', 'CKE+', 'RASn+', 'CASn+', 'WEn+',
'CSn0+']
return (buspins, inout, 'CLK')
def sys(suffix, bank):
return (['RST-', # reset line
+ 'PLLCLK-', # incoming clock (to PLL)
'PLLSELA0-', 'PLLSELA1-', # PLL divider-selector
- 'PLLCLK-', # incoming clock (to PLL)
'PLLTESTOUT+', # divided-output (for testing)
'PLLVCOUT+', # PLL VCO analog out (for testing)
], [], 'CLK')