# XXX TODO: correct these. this is a stub for now
# https://bugs.libre-soc.org/show_bug.cgi?id=303
def lpc(suffix, bank, pincount=4):
- lpcpins = ['CMD+', 'CLK+']
+ lpcpins = ['CMD*', 'CLK+']
inout = []
for i in range(pincount):
pname = "D%d*" % i
def emmc(suffix, bank, pincount=8):
- emmcpins = ['CMD+', 'CLK+']
+ emmcpins = ['CMD*', 'CLK+']
inout = []
for i in range(pincount):
pname = "D%d*" % i
def i2c(suffix, bank):
+ """bi-directional (reversible, master-slave) I2C
+ """
return (['SDA*', 'SCL*'], [], 'SCL')
+def mi2c(suffix, bank):
+ """master-only I2C (clock is output only)
+ """
+ return (['SDA*', 'SCL+'], [], 'SCL')
+
+
def jtag(suffix, bank):
return (['TMS-', 'TDI-', 'TDO+', 'TCK+'], [], 'TCK')
for i in range(10, 13):
buspins.append("AD%d+" % i)
for i in range(1, 2):
- pname = "DQM%d*" % i
+ pname = "DQM%d+" % i
buspins.append(pname)
for i in range(8, 16):
pname = "D%d*" % i
for i in range(13, 14):
buspins.append("AD%d+" % i)
for i in range(1, 4):
- pname = "DQM%d*" % i
+ pname = "DQM%d+" % i
for i in range(8, 32):
pname = "D%d*" % i
buspins.append(pname)
return (RangePin("-"), [], None)
def sys(suffix, bank):
- return (['CLK-', 'RST-', 'PLLCLK-', 'PLLOUT+',
- 'CSEL0-', 'CSEL1-', 'CSEL2-'], [], 'CLK')
+ return (['CLK-', # incoming clock (to PLL)
+ 'PLLSELA0-', 'PLLSELA1-', # PLL divider-selector
+ 'PLLTESTOUT+', # divided-output (for testing)
+ 'PLLVCOUT+', # PLL VCO analog out (for testing)
+ 'RST-', # reset line
+ ], [], 'CLK')
# list functions by name here
('SPI', spi),
('QSPI', quadspi),
('TWI', i2c),
+ ('MTWI', mi2c),
('JTAG', jtag),
('UART', uart),
('QUART', uartfull),