add missing clock to I2S pinfunction

[pinmux.git] / src / spec / pinfunctions.py

diff --git a/src/spec/pinfunctions.py b/src/spec/pinfunctions.py
index da3b912859e7bd0bab44e95c5cf86441977232ea..f1f9558a68005ecbd5dbf2f40f1465d07cd2146e 100644 (file)
--- a/src/spec/pinfunctions.py
+++ b/src/spec/pinfunctions.py
@@ -48,7 +48,7 @@
 
 def i2s(suffix, bank):
     return (['MCK+', 'BCK+', 'LRCK+', 'DI-', 'DO+'],
-            [])
+            [], "MCK")
 
 
 # XXX TODO: correct these.  this is a stub for now
@@ -197,10 +197,10 @@ def sdram1(suffix, bank, n_adr=10):
         pname = "D%d*" % i
         buspins.append(pname)
         inout.append(pname)
-    for i in range(n_adr):
-        buspins.append("AD%d+" % i)
     for i in range(2):
         buspins.append("BA%d+" % i)
+    for i in range(n_adr):
+        buspins.append("AD%d+" % i)
     buspins += ['CLK+', 'CKE+', 'RASn+', 'CASn+', 'WEn+',
                 'CSn0+']
     return (buspins, inout, 'CLK')
@@ -285,8 +285,12 @@ def vdd(suffix, bank):
     return (RangePin("-"), [], None)
 
 def sys(suffix, bank):
-    return (['CLK-', 'RST-', 'PLLCLK-', 'PLLOUT+',
-             'CSEL0-', 'CSEL1-', 'PLLOCK+'], [], 'CLK')
+    return (['RST-',                       # reset line
+             'PLLCLK-',                       # incoming clock (to PLL)
+             'PLLSELA0-', 'PLLSELA1-',     # PLL divider-selector
+             'PLLTESTOUT+',                # divided-output (for testing)
+             'PLLVCOUT+',                  # PLL VCO analog out (for testing)
+             ], [], 'CLK')
 
 # list functions by name here