def i2s(suffix, bank):
return (['MCK+', 'BCK+', 'LRCK+', 'DI-', 'DO+'],
- [])
+ [], "MCK")
# XXX TODO: correct these. this is a stub for now
pname = "D%d*" % i
buspins.append(pname)
inout.append(pname)
- for i in range(n_adr):
- buspins.append("AD%d+" % i)
for i in range(2):
buspins.append("BA%d+" % i)
+ for i in range(n_adr):
+ buspins.append("AD%d+" % i)
buspins += ['CLK+', 'CKE+', 'RASn+', 'CASn+', 'WEn+',
'CSn0+']
return (buspins, inout, 'CLK')
for i in range(10, 13):
buspins.append("AD%d+" % i)
for i in range(1, 2):
- pname = "DQM%d*" % i
+ pname = "DQM%d+" % i
buspins.append(pname)
for i in range(8, 16):
pname = "D%d*" % i
for i in range(13, 14):
buspins.append("AD%d+" % i)
for i in range(1, 4):
- pname = "DQM%d*" % i
+ pname = "DQM%d+" % i
for i in range(8, 32):
pname = "D%d*" % i
buspins.append(pname)
return (RangePin("-"), [], None)
def sys(suffix, bank):
- return (['CLK-', 'RST-', 'PLLCLK-', 'PLLOUT+',
- 'CSEL0-', 'CSEL1-', 'CSEL2-'], [], 'CLK')
+ return (['RST-', # reset line
+ 'PLLCLK-', # incoming clock (to PLL)
+ 'PLLSELA0-', 'PLLSELA1-', # PLL divider-selector
+ 'PLLTESTOUT+', # divided-output (for testing)
+ 'PLLVCOUT+', # PLL VCO analog out (for testing)
+ ], [], 'CLK')
# list functions by name here