return (RangePin("-"), [], None)
def sys(suffix, bank):
- return (['CLK-', 'RST-',
- 'PLLCLK-', # PLL ref clock input
+ return (['RST-', # reset line
'PLLSELA0-', 'PLLSELA1-', # PLL divider-selector
+ 'PLLCLK-', # incoming clock (to PLL)
'PLLTESTOUT+', # divided-output (for testing)
'PLLVCOUT+', # PLL VCO analog out (for testing)
], [], 'CLK')