move PLL around slightly, VCO on east top

[pinmux.git] / src / spec / pinfunctions.py

diff --git a/src/spec/pinfunctions.py b/src/spec/pinfunctions.py
index e3c97f3efa9bcacf8a990ad68888ab56d695cc01..f5f61d76c7410ac3045f5f332319ddde3bacbdc0 100644 (file)
--- a/src/spec/pinfunctions.py
+++ b/src/spec/pinfunctions.py
@@ -212,7 +212,7 @@ def sdram2(suffix, bank):
     for i in range(10, 13):
         buspins.append("AD%d+" % i)
     for i in range(1, 2):
-        pname = "DQM%d*" % i
+        pname = "DQM%d+" % i
         buspins.append(pname)
     for i in range(8, 16):
         pname = "D%d*" % i
@@ -229,7 +229,7 @@ def sdram3(suffix, bank):
     for i in range(13, 14):
         buspins.append("AD%d+" % i)
     for i in range(1, 4):
-        pname = "DQM%d*" % i
+        pname = "DQM%d+" % i
     for i in range(8, 32):
         pname = "D%d*" % i
         buspins.append(pname)
@@ -285,8 +285,12 @@ def vdd(suffix, bank):
     return (RangePin("-"), [], None)
 
 def sys(suffix, bank):
-    return (['CLK-', 'RST-', 'PLLCLK-', 'PLLOUT+',
-             'CSEL0-', 'CSEL1-', 'CSEL2-'], [], 'CLK')
+    return (['RST-',                       # reset line
+             'PLLSELA0-', 'PLLSELA1-',     # PLL divider-selector
+            'PLLCLK-',                       # incoming clock (to PLL)
+             'PLLTESTOUT+',                # divided-output (for testing)
+             'PLLVCOUT+',                  # PLL VCO analog out (for testing)
+             ], [], 'CLK')
 
 # list functions by name here