moved CLK away from testout

[pinmux.git] / src / spec / pinfunctions.py

diff --git a/src/spec/pinfunctions.py b/src/spec/pinfunctions.py
index d93f82a9769d3b46241621b878ae9c4f6c766445..f921f2b4a6f8c7c0ef59616c4db7a770089780f7 100644 (file)
--- a/src/spec/pinfunctions.py
+++ b/src/spec/pinfunctions.py
@@ -285,11 +285,11 @@ def vdd(suffix, bank):
     return (RangePin("-"), [], None)
 
 def sys(suffix, bank):
-    return (['PLLCLK-',                       # incoming clock (to PLL)
+    return (['RST-',                       # reset line
+             'PLLCLK-',                       # incoming clock (to PLL)
              'PLLSELA0-', 'PLLSELA1-',     # PLL divider-selector
              'PLLTESTOUT+',                # divided-output (for testing)
              'PLLVCOUT+',                  # PLL VCO analog out (for testing)
-             'RST-',                       # reset line
              ], [], 'CLK')
 
 # list functions by name here