spec.reg_wid = wordsize*8 # 32
self.bus = Record(make_wb_layout(spec), name="gpio_wb")
- #print("CSRBUS layout: ", csrbus_layout)
- # MultiCSR read and write buses
- temp = []
- for i in range(self.wordsize):
- temp_str = "rd_word{}".format(i)
- temp.append(Record(name=temp_str, layout=csrbus_layout))
- self.rd_multicsr = Array(temp)
-
- temp = []
- for i in range(self.wordsize):
- temp_str = "word{}".format(i)
- temp.append(Record(name=temp_str, layout=csrbus_layout))
- self.multicsrbus = Array(temp)
-
temp = []
for i in range(self.n_gpio):
- temp_str = "gpio{}".format(i)
- temp.append(Record(name=temp_str, layout=gpio_layout))
+ name = "gpio{}".format(i)
+ temp.append(Record(name=name, layout=gpio_layout))
self.gpio_ports = Array(temp)
def elaborate(self, platform):
wb_ack = bus.ack
gpio_ports = self.gpio_ports
- multi = self.multicsrbus
- rd_multi = self.rd_multicsr
- comb += wb_ack.eq(0)
+ # MultiCSR read and write buses
+ rd_multi = []
+ for i in range(self.wordsize):
+ name = "rd_word%d" % i
+ rd_multi.append(Record(name=name, layout=csrbus_layout))
- row_const = []
- for row in range(self.n_rows):
- row_const.append(Const(row))
+ wr_multi = []
+ for i in range(self.wordsize):
+ name = "wr_word%d" % i
+ wr_multi.append(Record(name=name, layout=csrbus_layout))
- # log2_int(1) will give 0, which wouldn't work?
- if (self.n_gpio == 1):
- row_start = Signal(1)
- else:
- row_start = Signal(log2_int(self.n_gpio))
+ # Combinatorial data reformarting for ease of connection
+ # Split the WB data into bytes for use with individual GPIOs
+ comb += Cat(*wr_multi).eq(wb_wr_data)
+ comb += wb_rd_data.eq(Cat(*rd_multi))
# Flag for indicating rd/wr transactions
new_transaction = Signal(1)
- #print("Types:")
- #print("gpio_addr: ", type(gpio_addr))
-
# One address used to configure CSR, set output, read input
with m.If(bus.cyc & bus.stb):
- comb += wb_ack.eq(1) # always ack
- # Probably wasteful
- sync += row_start.eq(bus.adr * self.wordsize)
sync += new_transaction.eq(1)
+
with m.If(bus.we): # write
- # Configure CSR
- for byte in range(0, self.wordsize):
- sync += multi[byte].eq(wb_wr_data[byte*8:8+byte*8])
- with m.Else(): # read
- # Concatinate the GPIO configs that are on the same "row" or
- # address and send
- multi_cat = []
- for i in range(0, self.wordsize):
- multi_cat.append(rd_multi[i])
- comb += wb_rd_data.eq(Cat(multi_cat))
+ sync += wb_ack.eq(1) # always ack, always delayed
+ with m.Else():
+ # Update the read multi bus with current GPIO configs
+ # not ack'ing as we need to wait 1 clk cycle before data ready
+ for i in range(len(bus.sel)):
+ GPIO_num = Signal(16) # fixed for now
+ comb += GPIO_num.eq(bus.adr*len(bus.sel)+i)
+ with m.If(bus.sel[i]):
+ sync += rd_multi[i].oe.eq(gpio_ports[GPIO_num].oe)
+ sync += rd_multi[i].ie.eq(~gpio_ports[GPIO_num].oe)
+ sync += rd_multi[i].puen.eq(gpio_ports[GPIO_num].puen)
+ sync += rd_multi[i].pden.eq(gpio_ports[GPIO_num].pden)
+ with m.If (gpio_ports[GPIO_num].oe):
+ sync += rd_multi[i].io.eq(gpio_ports[GPIO_num].o)
+ with m.Else():
+ sync += rd_multi[i].io.eq(gpio_ports[GPIO_num].i)
+ sync += rd_multi[i].bank.eq(gpio_ports[GPIO_num].bank)
+ with m.Else():
+ sync += rd_multi[i].oe.eq(0)
+ sync += rd_multi[i].ie.eq(0)
+ sync += rd_multi[i].puen.eq(0)
+ sync += rd_multi[i].pden.eq(0)
+ sync += rd_multi[i].io.eq(0)
+ sync += rd_multi[i].bank.eq(0)
with m.Else():
sync += new_transaction.eq(0)
+ sync += wb_ack.eq(0)
- # Only update GPIOs config if a new transaction happened last cycle
- # (read or write). Always lags from multi csrbus by 1 clk cycle, most
- # sane way I could think of while using Record().
+ # Delayed from the start of transaction by 1 clk cycle
with m.If(new_transaction):
- self.connect_wr_bus_to_gpio(m, sync, bus.adr, gpio_ports, multi)
- self.connect_gpio_to_rd_bus(m, sync, bus.adr, gpio_ports, rd_multi)
- #with m.Else():
- # print("Copy gpio_ports to multi...")
- # sync += multi[]
+ # Update the GPIO configs with sent parameters
+ with m.If(bus.we):
+ for i in range(len(bus.sel)):
+ GPIO_num = Signal(16) # fixed for now
+ comb += GPIO_num.eq(bus.adr*len(bus.sel)+i)
+ with m.If(bus.sel[i]):
+ sync += gpio_ports[GPIO_num].oe.eq(wr_multi[i].oe)
+ sync += gpio_ports[GPIO_num].puen.eq(wr_multi[i].puen)
+ sync += gpio_ports[GPIO_num].pden.eq(wr_multi[i].pden)
+ with m.If (wr_multi[i].oe):
+ sync += gpio_ports[GPIO_num].o.eq(wr_multi[i].io)
+ with m.Else():
+ sync += gpio_ports[GPIO_num].o.eq(0)
+ sync += gpio_ports[GPIO_num].bank.eq(wr_multi[i].bank)
+ sync += wb_ack.eq(0) # stop ack'ing!
+ # Copy the GPIO config data in read multi bus to the WB data bus
+ # Ack as we're done
+ with m.Else():
+ sync += wb_ack.eq(1) # Delay ack until rd data is ready!
return m
- def connect_wr_bus_to_gpio(self, module, domain, addr, gp, multi):
- if self.n_gpio > self.wordsize:
- print("#GPIOs is greater than, and is a multiple of WB wordsize")
- # Case where all gpios fit within full words
- if self.n_gpio % self.wordsize == 0:
- for row in range(self.n_rows):
- with module.If(addr == Const(row)):
- offset = row*self.wordsize
- for byte in range(self.wordsize):
- domain += gp[byte+offset].oe.eq(multi[byte].oe)
- domain += gp[byte+offset].puen.eq(multi[byte].puen)
- domain += gp[byte+offset].pden.eq(multi[byte].pden)
- # prevent output being set if GPIO configured as i
- # TODO: No checking is done if ie/oe high together
- with module.If(multi[byte].oe):
- domain += gp[byte+offset].o.eq(multi[byte].io)
- with module.Else():
- domain += multi[byte].io.eq(gp[byte+offset].i)
- domain += gp[byte+offset].bank.eq(multi[byte].bank)
- else:
- # TODO: This is a complex case, not needed atm
- print("#GPIOs is greater than WB wordsize")
- print("But not fully fitting in words...")
- print("NOT IMPLEMENTED THIS CASE")
- raise
- else:
- print("#GPIOs is less or equal to WB wordsize (in bytes)")
- for byte in range(self.n_gpio):
- domain += gp[byte].oe.eq(multi[byte].oe)
- domain += gp[byte].puen.eq(multi[byte].puen)
- domain += gp[byte].pden.eq(multi[byte].pden)
- # Check to prevent output being set if GPIO configured as i
- # TODO: No checking is done if ie/oe high together
- with module.If(multi[byte].oe):
- domain += gp[byte].o.eq(multi[byte].io)
- with module.Else():
- domain += gp[byte].o.eq(0)
- domain += gp[byte].bank.eq(multi[byte].bank)
-
- def connect_gpio_to_rd_bus(self, module, domain, addr, gp, multi):
- if self.n_gpio > self.wordsize:
- print("#GPIOs is greater than, and is a multiple of WB wordsize")
- # Case where all gpios fit within full words
- if self.n_gpio % self.wordsize == 0:
- for row in range(self.n_rows):
- with module.If(addr == Const(row)):
- offset = row*self.wordsize
- for byte in range(self.wordsize):
- domain += multi[byte].oe.eq(gp[byte+offset].oe)
- domain += multi[byte].puen.eq(gp[byte+offset].puen)
- domain += multi[byte].pden.eq(gp[byte+offset].pden)
- # prevent output being set if GPIO configured as i
- # TODO: No checking is done if ie/oe high together
- with module.If(gp[byte+offset].oe):
- domain += multi[byte].io.eq(gp[byte+offset].o)
- with module.Else():
- domain += multi[byte].io.eq(gp[byte+offset].i)
- domain += multi[byte].bank.eq(gp[byte+offset].bank)
- else:
- # TODO: This is a complex case, not needed atm
- print("#GPIOs is greater than WB wordsize")
- print("NOT IMPLEMENTED THIS CASE")
- raise
- else:
- print("#GPIOs is less or equal to WB wordsize (in bytes)")
- for byte in range(self.n_gpio):
- domain += multi[byte].oe.eq(gp[gpio].oe)
- domain += multi[byte].puen.eq(gp[gpio].puen)
- domain += multi[byte].pden.eq(gp[gpio].pden)
- # Check to prevent output being set if GPIO configured as i
- # TODO: No checking is done if ie/oe high together
- with module.If(multi[byte].oe):
- domain += multi[byte].io.eq(gp[gpio].o)
- with module.Else():
- domain += multi[byte].io.eq(gp[byte].i)
- domain += multi[byte].bank.eq(gp[gpio].bank)
-
-
def __iter__(self):
for field in self.bus.fields.values():
yield field
('gpio_wb__stb', 'in'),
('gpio_wb__we', 'in'),
('gpio_wb__adr[27:0]', 'in'),
+ ('gpio_wb__sel[3:0]', 'in'),
('gpio_wb__dat_w[{}:0]'.format(wb_data_width-1), 'in'),
('gpio_wb__dat_r[{}:0]'.format(wb_data_width-1), 'out'),
('gpio_wb__ack', 'out'),
gpio_internal_traces = ('Internal', [
('clk', 'in'),
('new_transaction'),
- ('row_start[2:0]'),
('rst', 'in')
])
traces.append(gpio_internal_traces)
- traces.append({'comment': 'Multi-byte GPIO config bus'})
+ traces.append({'comment': 'Multi-byte GPIO config read bus'})
+ for word in range(0, wordsize):
+ prefix = "rd_word{}__".format(word)
+ single_word = []
+ word_signals = []
+ single_word.append('Word{}'.format(word))
+ word_signals.append((prefix+'bank[{}:0]'.format(NUMBANKBITS-1)))
+ word_signals.append((prefix+'ie'))
+ word_signals.append((prefix+'io'))
+ word_signals.append((prefix+'oe'))
+ word_signals.append((prefix+'pden'))
+ word_signals.append((prefix+'puen'))
+ single_word.append(word_signals)
+ traces.append(tuple(single_word))
+
+ traces.append({'comment': 'Multi-byte GPIO config write bus'})
for word in range(0, wordsize):
- prefix = "word{}__".format(word)
+ prefix = "wr_word{}__".format(word)
single_word = []
word_signals = []
single_word.append('Word{}'.format(word))
#print(traces)
+ #module = "top.xics_icp"
+ module = "bench.top.xics_icp"
write_gtkw(filename+".gtkw", filename+".vcd", traces, style,
- module="top.xics_icp")
+ module=module)
def test_gpio():
filename = "test_gpio" # Doesn't include extension
gpios.print_info()
#gpios._parse_gpio_arg("all")
#gpios._parse_gpio_arg("0")
- gpios._parse_gpio_arg("1-3")
+ #gpios._parse_gpio_arg("1-3")
#gpios._parse_gpio_arg("20")
oe = 1
bank = 3
yield from gpios.config("0-3", oe=1, ie=0, puen=0, pden=1, outval=0, bank=2)
ie = 1
- yield from gpios.config("4-7", oe=0, ie=1, puen=0, pden=1, outval=0, bank=2)
- yield from gpios.set_out("0-3", outval=1)
+ yield from gpios.config("4-7", oe=0, ie=1, puen=0, pden=1, outval=0, bank=6)
+ yield from gpios.set_out("0-1", outval=1)
#yield from gpios.rd_all()
- yield from gpios.sim_set_in_pad("4-7", 1)
+ yield from gpios.sim_set_in_pad("6-7", 1)
print("----------------------------")
yield from gpios.rd_input("4-7")
projects / pinmux.git / blobdiff