class SimpleGPIO(Elaboratable):
def __init__(self, wordsize=4, n_gpio=16):
- print("SimpleGPIO: WB Data # of bytes: {0}, # of GPIOs: {1}"
- .format(wordsize, n_gpio))
self.wordsize = wordsize
self.n_gpio = n_gpio
+ self.n_rows = ceil(self.n_gpio / self.wordsize)
+ print("SimpleGPIO: WB Data # of bytes: {0}, #GPIOs: {1}, Rows: {2}"
+ .format(self.wordsize, self.n_gpio, self.n_rows))
class Spec: pass
spec = Spec()
spec.addr_wid = 30
spec.reg_wid = wordsize*8 # 32
self.bus = Record(make_wb_layout(spec), name="gpio_wb")
- #print("CSRBUS layout: ", csrbus_layout)
- # create array - probably a cleaner way to do this...
- temp = []
- for i in range(self.wordsize):
- temp_str = "word{}".format(i)
- temp.append(Record(name=temp_str, layout=csrbus_layout))
- self.multicsrbus = Array(temp)
-
temp = []
for i in range(self.n_gpio):
- temp_str = "gpio{}".format(i)
- temp.append(Record(name=temp_str, layout=gpio_layout))
+ name = "gpio{}".format(i)
+ temp.append(Record(name=name, layout=gpio_layout))
self.gpio_ports = Array(temp)
def elaborate(self, platform):
wb_ack = bus.ack
gpio_ports = self.gpio_ports
- multi = self.multicsrbus
- comb += wb_ack.eq(0)
+ # MultiCSR read and write buses
+ rd_multi = []
+ for i in range(self.wordsize):
+ name = "rd_word%d" % i
+ rd_multi.append(Record(name=name, layout=csrbus_layout))
- # log2_int(1) will give 0, which wouldn't work?
- if (self.n_gpio == 1):
- row_start = Signal(1)
- else:
- row_start = Signal(log2_int(self.n_gpio))
+ wr_multi = []
+ for i in range(self.wordsize):
+ name = "wr_word%d" % i
+ wr_multi.append(Record(name=name, layout=csrbus_layout))
+
+ # Connecting intermediate signals to the WB data buses
+ # allows the use of Records/Layouts
+ # Split the WB data into bytes for use with individual GPIOs
+ comb += Cat(*wr_multi).eq(wb_wr_data)
+ # Connect GPIO config bytes to form a single word
+ comb += wb_rd_data.eq(Cat(*rd_multi))
# Flag for indicating rd/wr transactions
new_transaction = Signal(1)
- #print("Types:")
- #print("gpio_addr: ", type(gpio_addr))
-
# One address used to configure CSR, set output, read input
with m.If(bus.cyc & bus.stb):
- comb += wb_ack.eq(1) # always ack
- # Probably wasteful
- sync += row_start.eq(bus.adr * self.wordsize)
sync += new_transaction.eq(1)
- with m.If(bus.we): # write
- # Configure CSR
- for byte in range(0, self.wordsize):
- sync += multi[byte].eq(wb_wr_data[byte*8:8+byte*8])
- with m.Else(): # read
- # Concatinate the GPIO configs that are on the same "row" or
- # address and send
- multi_cat = []
- for i in range(0, self.wordsize):
- multi_cat.append(multi[i])
- comb += wb_rd_data.eq(Cat(multi_cat))
+
+ with m.If(~bus.we): # read
+ # Update the read multi bus with current GPIO configs
+ # not ack'ing as we need to wait 1 clk cycle before data ready
+ for i in range(len(bus.sel)):
+ GPIO_num = Signal(16) # fixed for now
+ comb += GPIO_num.eq(bus.adr*len(bus.sel)+i)
+ with m.If(bus.sel[i]):
+ sync += rd_multi[i].oe.eq(gpio_ports[GPIO_num].oe)
+ sync += rd_multi[i].ie.eq(~gpio_ports[GPIO_num].oe)
+ sync += rd_multi[i].puen.eq(gpio_ports[GPIO_num].puen)
+ sync += rd_multi[i].pden.eq(gpio_ports[GPIO_num].pden)
+ with m.If (gpio_ports[GPIO_num].oe):
+ sync += rd_multi[i].io.eq(gpio_ports[GPIO_num].o)
+ with m.Else():
+ sync += rd_multi[i].io.eq(gpio_ports[GPIO_num].i)
+ sync += rd_multi[i].bank.eq(gpio_ports[GPIO_num].bank)
+ with m.Else():
+ sync += rd_multi[i].oe.eq(0)
+ sync += rd_multi[i].ie.eq(0)
+ sync += rd_multi[i].puen.eq(0)
+ sync += rd_multi[i].pden.eq(0)
+ sync += rd_multi[i].io.eq(0)
+ sync += rd_multi[i].bank.eq(0)
+ sync += wb_ack.eq(1) # ack after latching data
with m.Else():
sync += new_transaction.eq(0)
+ sync += wb_ack.eq(0)
- # Only update GPIOs config if a new transaction happened last cycle
- # (read or write). Always lags from multi csrbus by 1 clk cycle, most
- # sane way I could think of while using Record().
+ # Delayed from the start of transaction by 1 clk cycle
with m.If(new_transaction):
- # This is a complex case, not needed atm
- if self.n_gpio > self.wordsize:
- print("NOT IMPLEMENTED THIS CASE")
- """
- for byte in range(0, self.wordsize):
- if ((row_start+byte) < Const(self.n_gpio)):
- sync += gpio_ports[row+byte].oe.eq(multi[byte].oe)
- sync += gpio_ports[row+byte].puen.eq(multi[byte].puen)
- sync += gpio_ports[row+byte].pden.eq(multi[byte].pden)
- # prevent output being set if GPIO configured as i
- # TODO: No checking is done if ie/oe high together
- with m.If(gpio_ports[row+byte].oe):
- sync += gpio_ports[row+byte].o.eq(multi[byte].io)
+ # Update the GPIO configs with sent parameters
+ with m.If(bus.we):
+ for i in range(len(bus.sel)):
+ GPIO_num = Signal(16) # fixed for now
+ comb += GPIO_num.eq(bus.adr*len(bus.sel)+i)
+ with m.If(bus.sel[i]):
+ sync += gpio_ports[GPIO_num].oe.eq(wr_multi[i].oe)
+ sync += gpio_ports[GPIO_num].puen.eq(wr_multi[i].puen)
+ sync += gpio_ports[GPIO_num].pden.eq(wr_multi[i].pden)
+ with m.If (wr_multi[i].oe):
+ sync += gpio_ports[GPIO_num].o.eq(wr_multi[i].io)
with m.Else():
- sync += multi[byte].io.eq(gpio_ports[row+byte].i)
- sync += gpio_ports[row+byte].bank.eq(multi[byte].bank)
- """
- raise
- else:
- for byte in range(self.n_gpio):
- sync += gpio_ports[byte].oe.eq(multi[byte].oe)
- sync += gpio_ports[byte].puen.eq(multi[byte].puen)
- sync += gpio_ports[byte].pden.eq(multi[byte].pden)
- # Check to prevent output being set if GPIO configured as i
- # TODO: No checking is done if ie/oe high together
- with m.If(multi[byte].oe): # gpio_ports[byte].oe):
- sync += gpio_ports[byte].o.eq(multi[byte].io)
- with m.Else():
- sync += multi[byte].io.eq(gpio_ports[byte].i)
- sync += gpio_ports[byte].bank.eq(multi[byte].bank)
+ sync += gpio_ports[GPIO_num].o.eq(0)
+ sync += gpio_ports[GPIO_num].bank.eq(wr_multi[i].bank)
+ sync += wb_ack.eq(1) # ack after latching data
+ # No need as rd data is can be outputed on the first clk
+ # with m.Else():
+ # sync += wb_ack.eq(1) # Delay ack until rd data is ready!
return m
def __iter__(self):
def ports(self):
return list(self)
+"""
def gpio_test_in_pattern(dut, pattern):
num_gpios = len(dut.gpio_ports)
print("Test pattern:")
print(pattern)
for pat in range(0, len(pattern)):
for gpio in range(0, num_gpios):
- yield from gpio_set_in_pad(dut, gpio, pattern[pat])
+ yield gpio_set_in_pad(dut, gpio, pattern[pat])
yield
temp = yield from gpio_rd_input(dut, gpio)
print("Pattern: {0}, Reading {1}".format(pattern[pat], temp))
pat += 1
if pat == len(pattern):
break
+"""
def test_gpio_single(dut, gpio, use_random=True):
oe = 1
def __init__(self, shift_dict):
self.shift_dict = shift_dict
self.oe=0
- self.ie=0
+ self.ie=1 # By default gpio set as input
self.puen=0
self.pden=0
self.io=0
self.shift_dict = self._create_shift_dict()
self.n_gpios = len(self.dut.gpio_ports)
print(dir(self.dut))
- # Since GPIO HDL block already has wordsize parameter, use directly
- # Alternatively, can derive from WB data r/w buses (div by 8 for bytes)
- #self.wordsize = len(self.dut.gpio_wb__dat_w) / 8
- self.wordsize = self.dut.wordsize
- self.n_rows = ceil(self.n_gpios / self.wordsize)
+ # Get the number of bits of the WB sel signal
+ # indicates the number of gpios per address
+ self.n_gp_per_adr = len(self.dut.bus.sel)
+ # Shows if data is byte/half-word/word/qword addressable?
+ self.granuality = len(self.dut.bus.dat_w) // self.n_gp_per_adr
+ self.n_rows = ceil(self.n_gpios / self.n_gp_per_adr)
self.shadow_csr = []
for i in range(self.n_gpios):
self.shadow_csr.append(GPIOConfigReg(self.shift_dict))
def print_info(self):
print("----------")
print("GPIO Block Info:")
- print("Number of GPIOs: {}".format(self.n_gpios))
- print("WB Data bus width (in bytes): {}".format(self.wordsize))
- print("Number of rows: {}".format(self.n_rows))
+ print("Number of GPIOs: %d" % self.n_gpios)
+ print("GPIOs per WB data word: %d" % self.n_gp_per_adr)
+ print("WB data granuality: %d" % self.granuality)
+ print("Number of address rows: %d" % self.n_rows)
print("----------")
# The shifting of control bits in the configuration word is dependent on the
self.shadow_csr[gpio].set(oe, ie, puen, pden, io, bank)
return oe, ie, puen, pden, io, bank
- def rd_csr(self, row_start):
- row_word = yield from wb_read(self.wb_bus, row_start)
- print("Returned CSR: {0:x}".format(row_word))
- return row_word
-
- # Update a single row of configuration registers
- def wr_row(self, row_addr, check=False):
- curr_gpio = row_addr * self.wordsize
- config_word = 0
- for byte in range(0, self.wordsize):
- if curr_gpio >= self.n_gpios:
- break
- config_word += self.shadow_csr[curr_gpio].packed << (8 * byte)
- #print("Reading GPIO{} shadow reg".format(curr_gpio))
- curr_gpio += 1
- print("Writing shadow CSRs val {0:x} to row addr {1:x}"
- .format(config_word, row_addr))
- yield from wb_write(self.wb_bus, row_addr, config_word)
- yield # Allow one clk cycle to propagate
-
- if(check):
- read_word = yield from self.rd_row(row_addr)
- assert config_word == read_word
-
- # Read a single address row of GPIO CSRs, and update shadow
- def rd_row(self, row_addr):
- read_word = yield from self.rd_csr(row_addr)
- curr_gpio = row_addr * self.wordsize
- single_csr = 0
- for byte in range(0, self.wordsize):
- if curr_gpio >= self.n_gpios:
- break
- single_csr = (read_word >> (8 * byte)) & 0xFF
- #print("Updating GPIO{0} shadow reg to {1:x}"
- # .format(curr_gpio, single_csr))
- self.update_single_shadow(single_csr, curr_gpio)
- curr_gpio += 1
- return read_word
+ # Update multiple configuration registers
+ def wr(self, gp_start, gp_end, check=False):
+ # Some maths to determine how many transactions, and at which
+ # address to start transmitting
+ n_gp_config = gp_end - gp_start
+ adr_start = gp_start // self.n_gp_per_adr
+ n_adr = ceil(n_gp_config / self.n_gp_per_adr)
+
+ curr_gpio = gp_start
+ # cycle through addresses, each iteration is a WB tx
+ for adr in range(adr_start, adr_start + n_adr):
+ tx_sel = 0
+ tx_word = 0
+ # cycle through every WB sel bit, and add configs of
+ # corresponding gpios
+ for i in range(0, self.n_gp_per_adr):
+ # if current gpio's location in the WB data word matches sel bit
+ if (curr_gpio % self.n_gp_per_adr) == i:
+ print("gpio%d" % curr_gpio)
+ tx_sel += 1 << i
+ tx_word += (self.shadow_csr[curr_gpio].packed
+ << (self.granuality * i))
+ curr_gpio += 1
+ # stop if we processed all required gpios
+ if curr_gpio >= gp_end:
+ break
+ print("Adr: %x | Sel: %x | TX Word: %x" % (adr, tx_sel, tx_word))
+ yield from wb_write(self.wb_bus, adr, tx_word, tx_sel)
+ yield # Allow one clk cycle to propagate
+
+ if(check):
+ row_word = yield from wb_read(self.wb_bus, adr, tx_sel)
+ assert config_word == read_word
+
+ def rd(self, gp_start, gp_end):
+ # Some maths to determine how many transactions, and at which
+ # address to start transmitting
+ n_gp_config = gp_end - gp_start
+ adr_start = gp_start // self.n_gp_per_adr
+ n_adr = ceil(n_gp_config / self.n_gp_per_adr)
+
+ curr_gpio = gp_start
+ # cycle through addresses, each iteration is a WB tx
+ for adr in range(adr_start, adr_start + n_adr):
+ tx_sel = 0
+ # cycle through every WB sel bit, and add configs of
+ # corresponding gpios
+ for i in range(0, self.n_gp_per_adr):
+ # if current gpio's location in the WB data word matches sel bit
+ if (curr_gpio % self.n_gp_per_adr) == i:
+ print("gpio%d" % curr_gpio)
+ tx_sel += 1 << i
+ curr_gpio += 1
+ # stop if we processed all required gpios
+ if curr_gpio >= gp_end:
+ break
+ print("Adr: %x | Sel: %x " % (adr, tx_sel))
+ row_word = yield from wb_read(self.wb_bus, adr, tx_sel)
+
+ mask = (2**self.granuality) - 1
+ for i in range(self.n_gp_per_adr):
+ if ((tx_sel >> i) & 1) == 1:
+ single_csr = (row_word >> (i*self.granuality)) & mask
+ curr_gpio = adr*self.n_gp_per_adr + i
+ #print("rd gpio%d" % curr_gpio)
+ self.update_single_shadow(single_csr, curr_gpio)
# Write all shadow registers to GPIO block
def wr_all(self, check=False):
for row in range(0, self.n_rows):
- yield from self.wr_row(row, check)
+ yield from self.wr(0, self.n_gpios, check)
# Read all GPIO block row addresses and update shadow reg's
def rd_all(self, check=False):
for row in range(0, self.n_rows):
- yield from self.rd_row(row, check)
+ yield from self.rd(0, self.n_gpios)
def config(self, gpio_str, oe, ie, puen, pden, outval, bank, check=False):
start, end = self._parse_gpio_arg(gpio_str)
# print(oe, ie, puen, pden, outval, bank)
self.shadow_csr[gpio].set(oe, ie, puen, pden, outval, bank)
# TODO: only update the required rows?
- yield from self.wr_all()
+ #yield from self.wr_all()
+ yield from self.wr(start, end)
# Set/Clear the output bit for single or group of GPIOs
def set_out(self, gpio_str, outval):
print("Setting GPIOs {0}-{1} output to {2}"
.format(start, end-1, outval))
- yield from self.wr_all()
+ yield from self.wr(start, end)
- def rd_input(self, gpio_str): # REWORK
+ def rd_input(self, gpio_str):
start, end = self._parse_gpio_arg(gpio_str)
- curr_gpio = 0
- # Too difficult to think about, just read all configs
- #start_row = floor(start / self.wordsize)
- # Hack because end corresponds to range limit, but maybe on same row
- # TODO: clean
- #end_row = floor( (end-1) / self.wordsize) + 1
- read_data = [0] * self.n_rows
- for row in range(0, self.n_rows):
- read_data[row] = yield from self.rd_row(row)
+ #read_data = [0] * self.n_rows
+ #for row in range(0, self.n_rows):
+ # read_data[row] = yield from self.rd_row(row)
+ yield from self.rd(start, end)
num_to_read = (end - start)
read_in = [0] * num_to_read
read_in[i] = self.shadow_csr[curr_gpio].io
curr_gpio += 1
- print("GPIOs {0} until {1}, i={2}".format(start, end, read_in))
+ print("GPIOs %d until %d, i=%s".format(start, end, read_in))
return read_in
# TODO: There's probably a cleaner way to clear the bit...
('gpio_wb__stb', 'in'),
('gpio_wb__we', 'in'),
('gpio_wb__adr[27:0]', 'in'),
+ ('gpio_wb__sel[3:0]', 'in'),
('gpio_wb__dat_w[{}:0]'.format(wb_data_width-1), 'in'),
('gpio_wb__dat_r[{}:0]'.format(wb_data_width-1), 'out'),
('gpio_wb__ack', 'out'),
gpio_internal_traces = ('Internal', [
('clk', 'in'),
('new_transaction'),
- ('row_start[2:0]'),
('rst', 'in')
])
traces.append(gpio_internal_traces)
- traces.append({'comment': 'Multi-byte GPIO config bus'})
+ traces.append({'comment': 'Multi-byte GPIO config read bus'})
+ for word in range(0, wordsize):
+ prefix = "rd_word{}__".format(word)
+ single_word = []
+ word_signals = []
+ single_word.append('Word{}'.format(word))
+ word_signals.append((prefix+'bank[{}:0]'.format(NUMBANKBITS-1)))
+ word_signals.append((prefix+'ie'))
+ word_signals.append((prefix+'io'))
+ word_signals.append((prefix+'oe'))
+ word_signals.append((prefix+'pden'))
+ word_signals.append((prefix+'puen'))
+ single_word.append(word_signals)
+ traces.append(tuple(single_word))
+
+ traces.append({'comment': 'Multi-byte GPIO config write bus'})
for word in range(0, wordsize):
- prefix = "word{}__".format(word)
+ prefix = "wr_word{}__".format(word)
single_word = []
word_signals = []
single_word.append('Word{}'.format(word))
#print(traces)
+ #module = "top.xics_icp"
+ module = "bench.top.xics_icp"
write_gtkw(filename+".gtkw", filename+".vcd", traces, style,
- module="top.xics_icp")
+ module=module)
def test_gpio():
filename = "test_gpio" # Doesn't include extension
gpios.print_info()
#gpios._parse_gpio_arg("all")
#gpios._parse_gpio_arg("0")
- gpios._parse_gpio_arg("1-3")
+ #gpios._parse_gpio_arg("1-3")
#gpios._parse_gpio_arg("20")
oe = 1
pden = 1
outval = 0
bank = 3
- yield from gpios.config("0-3", oe=1, ie=0, puen=0, pden=1, outval=0, bank=2)
+ yield from gpios.config("0-1", oe=1, ie=0, puen=0, pden=1, outval=0, bank=2)
ie = 1
- yield from gpios.config("4-7", oe=0, ie=1, puen=0, pden=1, outval=0, bank=2)
- yield from gpios.set_out("0-3", outval=1)
+ yield from gpios.config("5-7", oe=0, ie=1, puen=0, pden=1, outval=0, bank=6)
+ yield from gpios.set_out("0-1", outval=1)
#yield from gpios.rd_all()
- yield from gpios.sim_set_in_pad("4-7", 1)
+ yield from gpios.sim_set_in_pad("6-7", 1)
print("----------------------------")
yield from gpios.rd_input("4-7")
projects / pinmux.git / blobdiff