jtag_set_shift_ir,
jtag_set_shift_dr,
jtag_set_run,
- jtag_set_idle)
+ jtag_set_idle,
+ tms_data_getset)
from c4m.nmigen.jtag.tap import TAP, IOType
from c4m.nmigen.jtag.bus import Interface as JTAGInterface
m.d.comb += gpio.gpio2.o.eq(gpio_o_test[2] ^ gpio.gpio2.i)
m.d.comb += gpio.gpio3.o.eq(gpio_o_test[3] ^ gpio.gpio3.i)
- m.d.comb += gpio.gpio0.oe.eq(gpio_oe_test[0])
- m.d.comb += gpio.gpio1.oe.eq(gpio_oe_test[1])
- m.d.comb += gpio.gpio2.oe.eq(gpio_oe_test[2])
- m.d.comb += gpio.gpio3.oe.eq(gpio_oe_test[3])
+ m.d.comb += gpio.gpio0.oe.eq(gpio_oe_test[0])# ^ gpio.gpio0.i)
+ m.d.comb += gpio.gpio1.oe.eq(gpio_oe_test[1])# ^ gpio.gpio1.i)
+ m.d.comb += gpio.gpio2.oe.eq(gpio_oe_test[2])# ^ gpio.gpio2.i)
+ m.d.comb += gpio.gpio3.oe.eq(gpio_oe_test[3])# ^ gpio.gpio3.i)
# get the UART resource, mess with the output tx
uart = self.jtag.request('uart')
print("uart fields", uart, uart.fields)
- self.intermediary = Signal()
- m.d.comb += uart.tx.eq(self.intermediary)
- m.d.comb += self.intermediary.eq(uart.rx)
+ self.uart_tx_test = Signal()
+ #self.intermediary = Signal()
+ #m.d.comb += uart.tx.eq(self.intermediary)
+ #m.d.comb += self.intermediary.eq(uart.rx)
+ # Allow tx to be controlled externally
+ m.d.comb += uart.tx.eq(self.uart_tx_test ^ uart.rx)
# I2C
num_i2c = 1
i2c = self.jtag.request('i2c')
print("i2c fields", i2c, i2c.fields)
# Connect in loopback
- m.d.comb += i2c.scl.o.eq(i2c.scl.i)
m.d.comb += i2c.sda.o.eq(i2c.sda.i)
+ m.d.comb += i2c.scl.o.eq(i2c.scl.i)
# Connect output enable to test port for sim
- m.d.comb += i2c.sda.oe.eq(i2c_sda_oe_test)
- m.d.comb += i2c.scl.oe.eq(i2c_scl_oe_test)
+ m.d.comb += i2c.sda.oe.eq(i2c_sda_oe_test)# ^ i2c.sda.i)
+ m.d.comb += i2c.scl.oe.eq(i2c_scl_oe_test)# ^ i2c.scl.i)
# to even be able to get at objects, you first have to make them
# available - i.e. not as local variables
# Public attributes are equivalent to input/output ports in hdl's
self.gpio = gpio
self.uart = uart
+ self.uart_tx_test
self.i2c = i2c
self.i2c_sda_oe_test = i2c_sda_oe_test
self.i2c_scl_oe_test = i2c_scl_oe_test
print("I2C Test PASSED!")
-
# JTAG boundary scan reg addresses - See c4m/nmigen/jtag/tap.py line #357
BS_EXTEST = 0
BS_INTEST = 0
BS_SAMPLE = 2
BS_PRELOAD = 2
-
def test_jtag_bs_chain(dut):
# print(dir(dut.jtag))
# print(dir(dut))
+ # print(dut.jtag._ir_width)
+ # print("JTAG I/O dictionary of core/pad signals:")
+ # print(dut.jtag.ios.keys())
print("JTAG BS Reset")
yield from jtag_set_reset(dut.jtag)
- #print("JTAG I/O dictionary of core/pad signals:")
- # print(dut.jtag.ios.keys())
-
+ # TODO: cleanup!
# Based on number of ios entries, produce a test shift reg pattern
bslen = len(dut.jtag.ios)
bsdata = 2**bslen - 1 # Fill with all 1s for now
fulldata = bsdata # for testing
emptydata = 0 # for testing
- mask_inputs = produce_ios_io_mask(dut, is_input=True)
- mask_outputs = produce_ios_io_mask(dut, is_input=False)
+ mask_i = produce_ios_mask(dut, is_i=True, is_o=False, is_oe=False)
+ mask_i_oe = produce_ios_mask(dut, is_i=True, is_o=False, is_oe=True)
+ mask_o = produce_ios_mask(dut, is_i=False, is_o=True, is_oe=False)
+ mask_oe = produce_ios_mask(dut, is_i=False, is_o=False, is_oe=True)
+ mask_o_oe = produce_ios_mask(dut, is_i=False, is_o=True, is_oe=True)
mask_low = 0
- mask_high = bsdata
+ mask_all = 2**bslen - 1
- # TODO: make format based on bslen, not a magic number 20-bits wide
- print("Input Mask: {0:20b}".format(mask_inputs))
- print("Output Mask: {0:20b}".format(mask_outputs))
+ num_bit_format = "{:0" + str(bslen) + "b}"
+ print("Masks (LSB corresponds to bit0 of the BS chain register!)")
+ print("Input only :", num_bit_format.format(mask_i))
+ print("Input and oe:", num_bit_format.format(mask_o_oe))
+ print("Output only :", num_bit_format.format(mask_o))
+ print("Out en only :", num_bit_format.format(mask_oe))
+ print("Output and oe:", num_bit_format.format(mask_o_oe))
- yield from jtag_unit_test(dut, BS_EXTEST, False, bsdata, mask_outputs)
- yield from jtag_unit_test(dut, BS_SAMPLE, False, bsdata, mask_low)
+ yield from jtag_unit_test(dut, BS_EXTEST, False, bsdata, mask_o_oe, mask_o)
+ yield from jtag_unit_test(dut, BS_SAMPLE, False, bsdata, mask_low, mask_low)
# Run through GPIO, UART, and I2C tests so that all signals are asserted
yield from test_gpios(dut)
yield from test_uart(dut)
yield from test_i2c(dut)
- yield from jtag_unit_test(dut, BS_EXTEST, True, emptydata, mask_inputs)
- yield from jtag_unit_test(dut, BS_SAMPLE, True, emptydata, mask_high)
+ bsdata = emptydata
+ yield from jtag_unit_test(dut, BS_EXTEST, True, bsdata, mask_i, mask_i_oe)
+ yield from jtag_unit_test(dut, BS_SAMPLE, True, bsdata, mask_all, mask_all)
print("JTAG Boundary Scan Chain Test PASSED!")
+# ONLY NEEDED FOR DEBUG - MAKE SURE TAP DRIVER FUNCTIONS CORRECT FIRST!
+def swap_bit_order(word, wordlen):
+ rev_word = 0
+ for i in range(wordlen):
+ rev_word += ((word >> i) & 0x1) << (wordlen-1-i)
-def jtag_unit_test(dut, bs_type, is_io_set, bsdata, expected):
- bslen = len(dut.jtag.ios)
+ num_bit_format = "{:0" + str(wordlen) + "b}"
+ print_str = "Orig:" + num_bit_format + " | Bit Swapped:" + num_bit_format
+ print(print_str.format(word, rev_word))
+
+ return rev_word
+
+def jtag_unit_test(dut, bs_type, is_io_set, bsdata, exp_pads, exp_tdo):
+ bslen = len(dut.jtag.ios) #* 2
+ print("Chain len based on jtag.ios: {}".format(bslen))
if bs_type == BS_EXTEST:
print("Sending TDI data with core/pads disconnected")
elif bs_type == BS_SAMPLE:
print("All pad inputs/core outputs reset, bs data: {0:b}"
.format(bsdata))
- result = yield from jtag_read_write_reg(dut.jtag, bs_type, bslen, bsdata)
+ result = yield from jtag_read_write_reg(dut.jtag, bs_type, bslen, bsdata,
+ reverse=True)
+ if bs_type == BS_EXTEST:
+ # TDO is only outputting previous BS chain data, must configure to
+ # output BS chain to the main shift register
+ yield from jtag_set_shift_dr(dut.jtag)
+ result = yield from tms_data_getset(dut.jtag, bs_type, bslen, bsdata,
+ reverse=True)
+ yield from jtag_set_idle(dut.jtag)
- # TODO: TDO data does not always match the signal states, maybe JTAG reset?
- print("TDI BS Data: {0:b}, Data Length (bits): {1}".format(bsdata, bslen))
- print("TDO BS Data: {0:b}".format(result))
- yield from check_ios_keys(dut, expected)
+ # TODO: make format based on bslen, not a magic number 20-bits wide
+ print("TDI BS Data: {0:020b}, Data Length (bits): {1}"
+ .format(bsdata, bslen))
+ print("TDO BS Data: {0:020b}".format(result))
+ yield from check_ios_keys(dut, result, exp_pads, exp_tdo)
+ #yield # testing extra clock
# Reset shift register between tests
yield from jtag_set_reset(dut.jtag)
-
-def check_ios_keys(dut, test_vector):
- print("Checking ios signals with given test vector")
+def check_ios_keys(dut, tdo_data, test_vector, exp_tdo):
+ print("Checking ios signals with TDO and given test vectors")
bslen = len(dut.jtag.ios)
ios_keys = list(dut.jtag.ios.keys())
+ print(" ios Signals | From TDO | --- | ----")
+ print("Side|Exp|Seen | Side|Exp|Seen | I/O | Name")
for i in range(0, bslen):
signal = ios_keys[i]
- test_value = (test_vector >> i) & 0b1
+ exp_pad_val = (test_vector >> i) & 0b1
+ exp_tdo_val = (exp_tdo >> i) & 0b1
+ tdo_value = (tdo_data >> i) & 0b1
# Only observed signals so far are outputs...
+ # TODO: Cleanup!
if check_if_signal_output(ios_keys[i]):
temp_result = yield dut.jtag.boundary_scan_pads[signal]['o']
- print("Core Output | Name: ", signal, " Value: ", temp_result)
+ print("Pad |{0:3b}|{1:4b} | Core|{2:3b}|{3:4b} | o | {4}"
+ .format(exp_pad_val, temp_result, exp_tdo_val, tdo_value, signal))
# ...or inputs
elif check_if_signal_input(ios_keys[i]):
temp_result = yield dut.jtag.boundary_scan_pads[signal]['i']
- print("Pad Input | Name: ", signal, " Value: ", temp_result)
+ print("Pad |{0:3b}|{1:4b} | Pad |{2:3b}|{3:4b} | i | {4}"
+ .format(exp_pad_val, temp_result, exp_tdo_val, tdo_value, signal))
else:
raise Exception("Signal in JTAG ios dict: " + signal
+ " cannot be determined as input or output!")
- assert temp_result == test_value
+ assert temp_result == exp_pad_val
+ assert tdo_value == exp_tdo_val
# TODO: may need to expand to support further signals contained in the
# JTAG module ios dictionary!
return False
-def produce_ios_io_mask(dut, is_input=False):
- if is_input:
+def produce_ios_mask(dut, is_i=False, is_o=True, is_oe=False):
+ if is_i and not(is_o) and not(is_oe):
mask_type = "input"
- else:
+ elif not(is_i) and is_o:
mask_type = "output"
+ else:
+ mask_type = "i={:b} | o={:b} | oe={:b} ".format(is_i, is_o, is_oe)
print("Determine the", mask_type, "mask")
bslen = len(dut.jtag.ios)
ios_keys = list(dut.jtag.ios.keys())
for i in range(0, bslen):
signal = ios_keys[i]
if (('__o' in ios_keys[i]) or ('__tx' in ios_keys[i])):
- if is_input == False:
- mask += (1 << i)
+ if ('__oe' in ios_keys[i]):
+ if is_oe:
+ mask += (1 << i)
+ else:
+ if is_o:
+ mask += (1 << i)
else:
- if is_input == True:
+ if is_i:
mask += (1 << i)
return mask
signal = ios_keys[i]
# Check if outputs are asserted
if ('__o' in ios_keys[i]) or ('__tx' in ios_keys[i]):
- print("Core Output | Name: ", signal)
+ print("Pad Output | Name: ", signal)
else:
- print("Pad Input | Name: ", signal)
+ print("Pad Input | Name: ", signal)
# Copied from test_jtag_tap.py
projects / pinmux.git / blobdiff