from soc.bus.sram import SRAM
from nmigen import Memory
-from nmigen.pysim import Simulator, Delay, Settle, Tick
+from nmigen.sim import Simulator, Delay, Settle, Tick
from nmutil.util import wrap
jtag_srv, jtag_set_reset,
jtag_set_ir, jtag_set_get_dr)
+from c4m.nmigen.jtag.tap import TAP, IOType
+from c4m.nmigen.jtag.bus import Interface as JTAGInterface
+from soc.debug.dmi import DMIInterface, DBGCore
+from soc.debug.test.dmi_sim import dmi_sim
+from soc.debug.test.jtagremote import JTAGServer, JTAGClient
+
# Was thinking of using these functions, but skipped for simplicity for now
# XXX nope. the output from JSON file.
#from pinfunctions import (i2s, lpc, emmc, sdmmc, mspi, mquadspi, spi,
m.d.comb += padpin.oe.eq(padport_oe)
return m
+ def toolchain_prepare(self, fragment, name, **kwargs):
+ """override toolchain_prepare in order to grab the fragment
+ """
+ self.fragment = fragment
+ return super().toolchain_prepare(fragment, name, **kwargs)
+
"""
and to create a Platform instance with that list, and build
resources = create_resources(pinset)
p = ASICPlatform (resources, top.jtag)
p.build(top)
+# this is what needs to gets treated as "top", after "main module" top
+# is augmented with IO pads with JTAG tacked on. the expectation that
+# the get_input() etc functions will be called magically by some other
+# function is unrealistic.
+top_fragment = p.fragment
+
+# XXX these modules are all being added *AFTER* the build process links
+# everything together. the expectation that this would work is... unrealistic.
+# ordering, clearly, is important.
# dut = JTAG(test_pinset(), wb_data_wid=64, domain="sync")
top.jtag.stop = False
# set up client-server on port 44843-something
top.jtag.s = JTAGServer()
-if len(sys.argv) != 2 or sys.argv[1] != 'server':
- cdut.c = JTAGClient()
- top.jtag.s.get_connection()
-else:
- print ("running server only as requested, use openocd remote to test")
- sys.stdout.flush()
- top.jtag.s.get_connection(None) # block waiting for connection
+cdut.c = JTAGClient()
+top.jtag.s.get_connection()
+#else:
+# print ("running server only as requested, use openocd remote to test")
+# sys.stdout.flush()
+# top.jtag.s.get_connection(None) # block waiting for connection
# take copy of ir_width and scan_len
cdut._ir_width = top.jtag._ir_width
cdut.scan_len = top.jtag.scan_len
memory = Memory(width=64, depth=16)
-sram = SRAM(memory=memory, bus=dut.wb)
+sram = SRAM(memory=memory, bus=top.jtag.wb)
#m = Module()
#m.submodules.ast = dut
#m.submodules.sram = sram
+# XXX simulating top (the module that does not itself contain IO pads
+# because that's covered by build) cannot possibly be expected to work
+# particularly when modules have been added *after* the platform build()
+# function has been called.
+
sim = Simulator(top)
sim.add_clock(1e-6, domain="sync") # standard clock
sim.add_sync_process(wrap(jtag_srv(top))) #? jtag server
-if len(sys.argv) != 2 or sys.argv[1] != 'server':
- sim.add_sync_process(wrap(jtag_sim(cdut, top.jtag))) # actual jtag tester
+#if len(sys.argv) != 2 or sys.argv[1] != 'server':
+sim.add_sync_process(wrap(jtag_sim(cdut, top.jtag))) # actual jtag tester
sim.add_sync_process(wrap(dmi_sim(top.jtag))) # handles (pretends to be) DMI
with sim.write_vcd("dmi2jtag_test_srv.vcd"):