from jtag import JTAG, resiotypes
from copy import deepcopy
+# extra dependencies for jtag testing (?)
+from soc.bus.sram import SRAM
+
+from nmigen import Memory
+from nmigen.sim import Simulator, Delay, Settle, Tick
+
+from nmutil.util import wrap
+
+from soc.debug.jtagutils import (jtag_read_write_reg,
+ jtag_srv, jtag_set_reset,
+ jtag_set_ir, jtag_set_get_dr)
+
+from c4m.nmigen.jtag.tap import TAP, IOType
+from c4m.nmigen.jtag.bus import Interface as JTAGInterface
+from soc.debug.dmi import DMIInterface, DBGCore
+from soc.debug.test.dmi_sim import dmi_sim
+from soc.debug.test.jtagremote import JTAGServer, JTAGClient
+
# Was thinking of using these functions, but skipped for simplicity for now
# XXX nope. the output from JSON file.
#from pinfunctions import (i2s, lpc, emmc, sdmmc, mspi, mquadspi, spi,
print (" pad", padres, padpin, padport, attrs)
print (" padpin", padpin.layout)
print (" jtag", io.core.layout, io.pad.layout)
- m.d.comb += padpin.i.eq(self._invert_if(invert, port))
+ m.d.comb += pin.i.eq(self._invert_if(invert, port))
+ m.d.comb += padpin.i.eq(padport)
m.d.comb += padport.io.eq(io.core.i)
- m.d.comb += pin.i.eq(io.pad.i)
+ m.d.comb += io.pad.i.eq(pin.i)
+
+ print("+=+=+= pin: ", pin)
+ print("+=+=+= port: ", port.layout)
+ print("+=+=+= pad pin: ", padpin)
+ print("+=+=+= pad port: ", padport)
return m
def get_output(self, pin, port, attrs, invert):
print (" pin", padpin.layout)
print (" jtag", io.core.layout, io.pad.layout)
m.d.comb += port.eq(self._invert_if(invert, pin.o))
- m.d.comb += padport.io.eq(io.core.o)
+ m.d.comb += padport.io.eq(self._invert_if(invert, padpin.o))
+ m.d.comb += io.core.o.eq(port.io)
m.d.comb += padpin.o.eq(io.pad.o)
return m
)
m.d.comb += pin.i.eq(self._invert_if(invert, port))
return m
- (res, pin, port, attrs) = self.padlookup[pin.name]
+ (padres, padpin, padport, padattrs) = self.padlookup[pin.name]
io = self.jtag.ios[pin.name]
- print (" pad", res, pin, port, attrs)
- print (" pin", pin.layout)
+ print (" pad", padres, padpin, padport, padattrs)
+ print (" pin", padpin.layout)
print (" port layout", port.layout)
print (" jtag", io.core.layout, io.pad.layout)
#m.submodules += Instance("$tribuf",
# i_A=self._invert_if(invert, io.pad.o),
# o_Y=port,
#)
+ # Create aliases for the port sub-signals
port_i = port.io[0]
port_o = port.io[1]
port_oe = port.io[2]
- m.d.comb += io.pad.i.eq(self._invert_if(invert, port_i))
- m.d.comb += port_o.eq(self._invert_if(invert, io.pad.o))
- m.d.comb += port_oe.eq(io.pad.o)
- m.d.comb += pin.i.eq(io.core.i)
- m.d.comb += io.core.o.eq(pin.o)
- m.d.comb += io.core.oe.eq(pin.oe)
+
+ padport_i = padport.io[0]
+ padport_o = padport.io[1]
+ padport_oe = padport.io[2]
+
+ # Connect SoC pins to SoC port
+ m.d.comb += pin.i.eq(port_i)
+ m.d.comb += port_o.eq(pin.o)
+ m.d.comb += port_oe.eq(pin.oe)
+ # Connect SoC port to JTAG io.core side
+ m.d.comb += port_i.eq(io.core.i)
+ m.d.comb += io.core.o.eq(port_o)
+ m.d.comb += io.core.oe.eq(port_oe)
+ # Connect JTAG io.pad side to pad port
+ m.d.comb += io.pad.i.eq(padport_i)
+ m.d.comb += padport_o.eq(io.pad.o)
+ m.d.comb += padport_oe.eq(io.pad.oe)
+ # Connect pad port to pad pins
+ m.d.comb += padport_i.eq(padpin.i)
+ m.d.comb += padpin.o.eq(padport_o)
+ m.d.comb += padpin.oe.eq(padport_oe)
return m
+ def toolchain_prepare(self, fragment, name, **kwargs):
+ """override toolchain_prepare in order to grab the fragment
+ """
+ self.fragment = fragment
+ return super().toolchain_prepare(fragment, name, **kwargs)
+
"""
and to create a Platform instance with that list, and build
resources = create_resources(pinset)
p = ASICPlatform (resources, top.jtag)
p.build(top)
-
+# this is what needs to gets treated as "top", after "main module" top
+# is augmented with IO pads with JTAG tacked on. the expectation that
+# the get_input() etc functions will be called magically by some other
+# function is unrealistic.
+top_fragment = p.fragment
+
+# XXX these modules are all being added *AFTER* the build process links
+# everything together. the expectation that this would work is... unrealistic.
+# ordering, clearly, is important.
+
+# dut = JTAG(test_pinset(), wb_data_wid=64, domain="sync")
+top.jtag.stop = False
+# rather than the client access the JTAG bus directly
+# create an alternative that the client sets
+class Dummy: pass
+cdut = Dummy()
+cdut.cbus = JTAGInterface()
+
+# set up client-server on port 44843-something
+top.jtag.s = JTAGServer()
+cdut.c = JTAGClient()
+top.jtag.s.get_connection()
+#else:
+# print ("running server only as requested, use openocd remote to test")
+# sys.stdout.flush()
+# top.jtag.s.get_connection(None) # block waiting for connection
+
+# take copy of ir_width and scan_len
+cdut._ir_width = top.jtag._ir_width
+cdut.scan_len = top.jtag.scan_len
+
+memory = Memory(width=64, depth=16)
+sram = SRAM(memory=memory, bus=top.jtag.wb)
+
+#m = Module()
+#m.submodules.ast = dut
+#m.submodules.sram = sram
+
+# XXX simulating top (the module that does not itself contain IO pads
+# because that's covered by build) cannot possibly be expected to work
+# particularly when modules have been added *after* the platform build()
+# function has been called.
+
+sim = Simulator(top)
+sim.add_clock(1e-6, domain="sync") # standard clock
+
+sim.add_sync_process(wrap(jtag_srv(top))) #? jtag server
+#if len(sys.argv) != 2 or sys.argv[1] != 'server':
+sim.add_sync_process(wrap(jtag_sim(cdut, top.jtag))) # actual jtag tester
+sim.add_sync_process(wrap(dmi_sim(top.jtag))) # handles (pretends to be) DMI
+
+with sim.write_vcd("dmi2jtag_test_srv.vcd"):
+ sim.run()
projects / pinmux.git / blobdiff