from jtag import JTAG, resiotypes
from copy import deepcopy
+# extra dependencies for jtag testing (?)
+from soc.bus.sram import SRAM
+
+from nmigen import Memory
+from nmigen.sim import Simulator, Delay, Settle, Tick
+
+from nmutil.util import wrap
+
+from soc.debug.jtagutils import (jtag_read_write_reg,
+ jtag_srv, jtag_set_reset,
+ jtag_set_ir, jtag_set_get_dr)
+
+from c4m.nmigen.jtag.tap import TAP, IOType
+from c4m.nmigen.jtag.bus import Interface as JTAGInterface
+from soc.debug.dmi import DMIInterface, DBGCore
+from soc.debug.test.dmi_sim import dmi_sim
+from soc.debug.test.jtagremote import JTAGServer, JTAGClient
+from nmigen.build.res import ResourceError
+
# Was thinking of using these functions, but skipped for simplicity for now
# XXX nope. the output from JSON file.
#from pinfunctions import (i2s, lpc, emmc, sdmmc, mspi, mquadspi, spi,
gpios.append("%d*" % i)
return {'uart': ['tx+', 'rx-'],
'gpio': gpios,
+ #'jtag': ['tms-', 'tdi-', 'tdo+', 'tck+'],
'i2c': ['sda*', 'scl+']}
"""
ios = []
for pin in pins:
pname = "gpio"+pin[:-1] # strip "*" on end
- pads = []
# urrrr... tristsate and io assume a single pin which is
# of course exactly what we don't want in an ASIC: we want
# *all three* pins but the damn port is not outputted
# as a triplet, it's a single Record named "io". sigh.
# therefore the only way to get a triplet of i/o/oe
# is to *actually* create explicit triple pins
- pads.append(Subsignal("i",
- Pins(pname+"_i", dir="i", assert_width=1)))
- pads.append(Subsignal("o",
- Pins(pname+"_o", dir="o", assert_width=1)))
- pads.append(Subsignal("oe",
- Pins(pname+"_oe", dir="oe", assert_width=1)))
- ios.append(Resource.family(pname, 0, default_name=pname,
- ios=pads))
+ pad = Subsignal("io",
+ Pins("%s_i %s_o %s_oe" % (pname, pname, pname),
+ dir="io", assert_width=3))
+ ios.append(Resource(pname, 0, pad))
resources.append(Resource.family(periph, 0, default_name="gpio",
ios=ios))
return resources
+def JTAGResource(*args):
+ io = []
+ io.append(Subsignal("tms", Pins("tms", dir="i", assert_width=1)))
+ io.append(Subsignal("tdi", Pins("tdi", dir="i", assert_width=1)))
+ io.append(Subsignal("tck", Pins("tck", dir="i", assert_width=1)))
+ io.append(Subsignal("tdo", Pins("tdo", dir="o", assert_width=1)))
+ return Resource.family(*args, default_name="jtag", ios=io)
+
def UARTResource(*args, rx, tx):
io = []
io.append(Subsignal("rx", Pins(rx, dir="i", assert_width=1)))
class Blinker(Elaboratable):
def __init__(self, pinset):
self.jtag = JTAG({}, "sync")
+ self.jtag.core_mgr = ResourceManager([], [])
+ memory = Memory(width=32, depth=16)
+ self.sram = SRAM(memory=memory, bus=self.jtag.wb)
def elaborate(self, platform):
m = Module()
m.submodules.jtag = self.jtag
+ m.submodules.sram = self.sram
+
count = Signal(5)
m.d.sync += count.eq(5)
print ("resources", platform.resources.items())
gpio = platform.request('gpio')
print (gpio, gpio.layout, gpio.fields)
# get the GPIO bank, mess about with some of the pins
- m.d.comb += gpio.gpio0.o.eq(1)
- m.d.comb += gpio.gpio1.o.eq(gpio.gpio2.i)
- m.d.comb += gpio.gpio1.oe.eq(count[4])
- m.d.sync += count[0].eq(gpio.gpio1.i)
+ m.d.comb += gpio.gpio0.io.o.eq(1)
+ m.d.comb += gpio.gpio1.io.o.eq(gpio.gpio2.io.i)
+ m.d.comb += gpio.gpio1.io.oe.eq(count[4])
+ m.d.sync += count[0].eq(gpio.gpio1.io.i)
# get the UART resource, mess with the output tx
uart = platform.request('uart')
print (uart, uart.fields)
- m.d.comb += uart.tx.eq(1)
+ intermediary = Signal()
+ m.d.comb += uart.tx.eq(intermediary)
+ m.d.comb += intermediary.eq(uart.rx)
+
+ # wire up JTAG otherwise we are in trouble (no clock)
+ jtag = platform.request('jtag')
+ m.d.comb += self.jtag.bus.tdi.eq(jtag.tdi)
+ m.d.comb += self.jtag.bus.tck.eq(jtag.tck)
+ m.d.comb += self.jtag.bus.tms.eq(jtag.tms)
+ m.d.comb += jtag.tdo.eq(self.jtag.bus.tdo)
+
return m
connectors = []
resources = OrderedDict()
required_tools = []
- command_templates = ['/bin/true']
+ command_templates = ['/bin/true'] # no command needed: stops barfing
file_templates = {
**TemplatedPlatform.build_script_templates,
"{{name}}.il": r"""
default_rst = "rst" # should be picked up / overridden by platform sys.rst
def __init__(self, resources, jtag):
- self.pad_mgr = ResourceManager([], [])
self.jtag = jtag
super().__init__()
+
# create set of pin resources based on the pinset, this is for the core
self.add_resources(resources)
# record resource lookup between core IO names and pads
self.padlookup = {}
+ # add JTAG without scan
+ self.add_resources([JTAGResource('jtag', 0)], no_boundary_scan=True)
+
def request(self, name, number=0, *, dir=None, xdr=None):
"""request a Resource (e.g. name="uart", number=0) which will
return a data structure containing Records of all the pins.
this override will also - automatically - create a JTAG Boundary Scan
connection *without* any change to the actual Platform.request() API
"""
+ core_mgr = self.jtag.core_mgr
# okaaaay, bit of shenanigens going on: the important data structure
# here is Resourcemanager._ports. requests add to _ports, which is
# what needs redirecting. therefore what has to happen is to
# now make a corresponding (duplicate) request to the pad manager
# BUT, if it doesn't exist, don't sweat it: all it means is, the
# application did not request Boundary Scan for that resource.
- pad_start_ports = len(self.pad_mgr._ports)
+ pad_start_ports = len(core_mgr._ports)
try:
- pvalue = self.pad_mgr.request(name, number, dir=dir, xdr=xdr)
- except AssertionError:
+ pvalue = core_mgr.request(name, number, dir=dir, xdr=xdr)
+ except ResourceError:
return value
- pad_end_ports = len(self.pad_mgr._ports)
+ pad_end_ports = len(core_mgr._ports)
# ok now we have the lengths: now create a lookup between the pad
# and the core, so that JTAG boundary scan can be inserted in between
core = self._ports[start_ports:end_ports]
- pads = self.pad_mgr._ports[pad_start_ports:pad_end_ports]
+ pads = core_mgr._ports[pad_start_ports:pad_end_ports]
# oops if not the same numbers added. it's a duplicate. shouldn't happen
assert len(core) == len(pads), "argh, resource manager error"
print ("core", core)
if pin is None: continue # skip when pin is None
assert corepin is not None # if pad was None, core should be too
print ("iter", pad, pin.name)
+ print ("existing pads", self.padlookup.keys())
assert pin.name not in self.padlookup # no overwrites allowed!
assert pin.name == corepin.name # has to be the same!
self.padlookup[pin.name] = pad # store pad by pin name
return
# make a *second* - identical - set of pin resources for the IO ring
padres = deepcopy(resources)
- self.pad_mgr.add_resources(padres)
+ self.jtag.core_mgr.add_resources(padres)
+
+ #def iter_ports(self):
+ # yield from super().iter_ports()
+ # for io in self.jtag.ios.values():
+ # print ("iter ports", io.layout, io)
+ # for field in io.core.fields:
+ # yield getattr(io.core, field)
+ # for field in io.pad.fields:
+ # yield getattr(io.pad, field)
# XXX these aren't strictly necessary right now but the next
# phase is to add JTAG Boundary Scan so it maaay be worth adding?
def get_input(self, pin, port, attrs, invert):
self._check_feature("single-ended input", pin, attrs,
valid_xdrs=(0,), valid_attrs=None)
- # Create a module first
- m=Module()
+
+ m = Module()
print (" get_input", pin, "port", port, port.layout)
- if pin.name not in ['clk_0', 'rst_0']: # sigh
- (res, pin, port, attrs) = self.padlookup[pin.name]
- io = self.jtag.ios[pin.name]
- print (" pad", res, pin, port, attrs)
- print (" pin", pin.layout)
- print (" jtag", io.core.layout, io.pad.layout)
- # Layout basically contains the list of objects (and sizes)
- # so a Layout of [('i', 1)] means, "this object has a Signal
- # named i and it is of length 1". threfore:
- # * pin has a pin.i of length 1
- # * io.core has an io.core.i of length 1
- # * io.pad has an io.pad.i of length 1
- # Your Mission, Should You Choose To Accept It, is to
- # work out which bleeding way round what the hell is
- # connected to what.
- m.d.comb += io.pad.i.eq(self._invert_if(invert, port))
- m.d.comb += pin.i.eq(io.core.i)
- else: # simple pass-through from port to pin
+ if pin.name in ['clk_0', 'rst_0']: # sigh
+ # simple pass-through from port to pin
print("No JTAG chain in-between")
m.d.comb += pin.i.eq(self._invert_if(invert, port))
+ return m
+ if pin.name not in self.padlookup:
+ print("No pin named %s, not connecting to JTAG BS" % pin.name)
+ m.d.comb += pin.i.eq(self._invert_if(invert, port))
+ return m
+ (padres, padpin, padport, padattrs) = self.padlookup[pin.name]
+ io = self.jtag.ios[pin.name]
+ print (" pad", padres, padpin, padport, attrs)
+ print (" padpin", padpin.layout)
+ print (" jtag", io.core.layout, io.pad.layout)
+ m.d.comb += pin.i.eq(self._invert_if(invert, port))
+ m.d.comb += padpin.i.eq(padport)
+ m.d.comb += padport.io.eq(io.core.i)
+ m.d.comb += io.pad.i.eq(pin.i)
+
+ print("+=+=+= pin: ", pin)
+ print("+=+=+= port: ", port.layout)
+ print("+=+=+= pad pin: ", padpin)
+ print("+=+=+= pad port: ", padport)
return m
def get_output(self, pin, port, attrs, invert):
self._check_feature("single-ended output", pin, attrs,
valid_xdrs=(0,), valid_attrs=None)
- print (" get_output", pin, "port", port, port.layout)
m = Module()
+ print (" get_output", pin, "port", port, port.layout)
+ if pin.name in ['clk_0', 'rst_0']: # sigh
+ # simple pass-through from pin to port
+ print("No JTAG chain in-between")
+ m.d.comb += port.eq(self._invert_if(invert, pin.o))
+ return m
+ if pin.name not in self.padlookup:
+ print("No pin named %s, not connecting to JTAG BS" % pin.name)
+ m.d.comb += port.eq(self._invert_if(invert, pin.o))
+ return m
+ (padres, padpin, padport, padattrs) = self.padlookup[pin.name]
+ io = self.jtag.ios[pin.name]
+ print (" pad", padres, padpin, padport, padattrs)
+ print (" pin", padpin.layout)
+ print (" jtag", io.core.layout, io.pad.layout)
m.d.comb += port.eq(self._invert_if(invert, pin.o))
+ m.d.comb += padport.io.eq(padpin.o)
+ m.d.comb += io.core.o.eq(port.io)
+ m.d.comb += padpin.o.eq(io.pad.o)
return m
def get_tristate(self, pin, port, attrs, invert):
self._check_feature("single-ended tristate", pin, attrs,
valid_xdrs=(0,), valid_attrs=None)
+ print (" get_tristate", pin, "port", port, port.layout)
m = Module()
- m.submodules += Instance("$tribuf",
- p_WIDTH=pin.width,
- i_EN=pin.oe,
- i_A=self._invert_if(invert, pin.o),
- o_Y=port,
- )
+ if pin.name in ['clk_0', 'rst_0']: # sigh
+ print("No JTAG chain in-between")
+ m.submodules += Instance("$tribuf",
+ p_WIDTH=pin.width,
+ i_EN=pin.oe,
+ i_A=self._invert_if(invert, pin.o),
+ o_Y=port,
+ )
+ return m
+ (res, pin, port, attrs) = self.padlookup[pin.name]
+ io = self.jtag.ios[pin.name]
+ print (" pad", res, pin, port, attrs)
+ print (" pin", pin.layout)
+ print (" jtag", io.core.layout, io.pad.layout)
+ #m.submodules += Instance("$tribuf",
+ # p_WIDTH=pin.width,
+ # i_EN=io.pad.oe,
+ # i_A=self._invert_if(invert, io.pad.o),
+ # o_Y=port,
+ #)
+ m.d.comb += io.core.o.eq(pin.o)
+ m.d.comb += io.core.oe.eq(pin.oe)
+ m.d.comb += pin.i.eq(io.core.i)
+ m.d.comb += io.pad.i.eq(port.i)
+ m.d.comb += port.o.eq(io.pad.o)
+ m.d.comb += port.oe.eq(io.pad.oe)
return m
def get_input_output(self, pin, port, attrs, invert):
self._check_feature("single-ended input/output", pin, attrs,
valid_xdrs=(0,), valid_attrs=None)
+
print (" get_input_output", pin, "port", port, port.layout)
m = Module()
- m.submodules += Instance("$tribuf",
- p_WIDTH=pin.width,
- i_EN=pin.oe,
- i_A=self._invert_if(invert, pin.o),
- o_Y=port,
- )
- m.d.comb += pin.i.eq(self._invert_if(invert, port))
+ if pin.name in ['clk_0', 'rst_0']: # sigh
+ print("No JTAG chain in-between")
+ m.submodules += Instance("$tribuf",
+ p_WIDTH=pin.width,
+ i_EN=pin.oe,
+ i_A=self._invert_if(invert, pin.o),
+ o_Y=port,
+ )
+ m.d.comb += pin.i.eq(self._invert_if(invert, port))
+ return m
+ (padres, padpin, padport, padattrs) = self.padlookup[pin.name]
+ io = self.jtag.ios[pin.name]
+ print (" pad", padres, padpin, padport, padattrs)
+ print (" pin", padpin.layout)
+ print (" port layout", port.layout)
+ print (" jtag", io.core.layout, io.pad.layout)
+ #m.submodules += Instance("$tribuf",
+ # p_WIDTH=pin.width,
+ # i_EN=io.pad.oe,
+ # i_A=self._invert_if(invert, io.pad.o),
+ # o_Y=port,
+ #)
+ # Create aliases for the port sub-signals
+ port_i = port.io[0]
+ port_o = port.io[1]
+ port_oe = port.io[2]
+
+ padport_i = padport.io[0]
+ padport_o = padport.io[1]
+ padport_oe = padport.io[2]
+
+ # Connect SoC pins to SoC port
+ m.d.comb += pin.i.eq(port_i)
+ m.d.comb += port_o.eq(pin.o)
+ m.d.comb += port_oe.eq(pin.oe)
+ # Connect SoC port to JTAG io.core side
+ m.d.comb += port_i.eq(io.core.i)
+ m.d.comb += io.core.o.eq(port_o)
+ m.d.comb += io.core.oe.eq(port_oe)
+ # Connect JTAG io.pad side to pad port
+ m.d.comb += io.pad.i.eq(padport_i)
+ m.d.comb += padport_o.eq(io.pad.o)
+ m.d.comb += padport_oe.eq(io.pad.oe)
+ # Connect pad port to pad pins
+ m.d.comb += padport_i.eq(padpin.i)
+ m.d.comb += padpin.o.eq(padport_o)
+ m.d.comb += padpin.oe.eq(padport_oe)
return m
+ def toolchain_prepare(self, fragment, name, **kwargs):
+ """override toolchain_prepare in order to grab the fragment
+ """
+ self.fragment = fragment
+ return super().toolchain_prepare(fragment, name, **kwargs)
"""
and to create a Platform instance with that list, and build
"""
pinset = dummy_pinset()
top = Blinker(pinset)
+
+
+# XXX these modules are all being added *AFTER* the build process links
+# everything together. the expectation that this would work is... unrealistic.
+# ordering, clearly, is important.
+
+# dut = JTAG(test_pinset(), wb_data_wid=64, domain="sync")
+top.jtag.stop = False
+# rather than the client access the JTAG bus directly
+# create an alternative that the client sets
+class Dummy: pass
+cdut = Dummy()
+cdut.cbus = JTAGInterface()
+
+# set up client-server on port 44843-something
+top.jtag.s = JTAGServer()
+cdut.c = JTAGClient()
+top.jtag.s.get_connection()
+#else:
+# print ("running server only as requested, use openocd remote to test")
+# sys.stdout.flush()
+# top.jtag.s.get_connection(None) # block waiting for connection
+
+# take copy of ir_width and scan_len
+cdut._ir_width = top.jtag._ir_width
+cdut.scan_len = top.jtag.scan_len
+
print(pinset)
resources = create_resources(pinset)
p = ASICPlatform (resources, top.jtag)
p.build(top)
-
+# this is what needs to gets treated as "top", after "main module" top
+# is augmented with IO pads with JTAG tacked on. the expectation that
+# the get_input() etc functions will be called magically by some other
+# function is unrealistic.
+top_fragment = p.fragment
+
+# XXX simulating top (the module that does not itself contain IO pads
+# because that's covered by build) cannot possibly be expected to work
+# particularly when modules have been added *after* the platform build()
+# function has been called.
+
+sim = Simulator(top_fragment)
+sim.add_clock(1e-6, domain="sync") # standard clock
+
+sim.add_sync_process(wrap(jtag_srv(top))) #? jtag server
+#if len(sys.argv) != 2 or sys.argv[1] != 'server':
+sim.add_sync_process(wrap(jtag_sim(cdut, top.jtag))) # actual jtag tester
+sim.add_sync_process(wrap(dmi_sim(top.jtag))) # handles (pretends to be) DMI
+
+with sim.write_vcd("dmi2jtag_test_srv.vcd"):
+ sim.run()
projects / pinmux.git / blobdiff