sort out ordering of modules

[pinmux.git] / src / spec / testing_stage1.py

diff --git a/src/spec/testing_stage1.py b/src/spec/testing_stage1.py
index f7dc99ca31f912cb0d82c43d769f6db229412873..33d79b5e3fa6ffb3e4ca2e401103ab2fbad4e1b3 100644 (file)
--- a/src/spec/testing_stage1.py
+++ b/src/spec/testing_stage1.py
@@ -7,6 +7,24 @@ from collections import OrderedDict
 from jtag import JTAG, resiotypes
 from copy import deepcopy
 
+# extra dependencies for jtag testing (?)
+from soc.bus.sram import SRAM
+
+from nmigen import Memory
+from nmigen.sim import Simulator, Delay, Settle, Tick
+
+from nmutil.util import wrap
+
+from soc.debug.jtagutils import (jtag_read_write_reg,
+                                 jtag_srv, jtag_set_reset,
+                                 jtag_set_ir, jtag_set_get_dr)
+
+from c4m.nmigen.jtag.tap import TAP, IOType
+from c4m.nmigen.jtag.bus import Interface as JTAGInterface
+from soc.debug.dmi import DMIInterface, DBGCore
+from soc.debug.test.dmi_sim import dmi_sim
+from soc.debug.test.jtagremote import JTAGServer, JTAGClient
+
 # Was thinking of using these functions, but skipped for simplicity for now
 # XXX nope.  the output from JSON file.
 #from pinfunctions import (i2s, lpc, emmc, sdmmc, mspi, mquadspi, spi,
@@ -95,10 +113,15 @@ def I2CResource(*args, scl, sda):
 class Blinker(Elaboratable):
     def __init__(self, pinset):
         self.jtag = JTAG({}, "sync")
+        memory = Memory(width=32, depth=16)
+        self.sram = SRAM(memory=memory, bus=self.jtag.wb)
+
 
     def elaborate(self, platform):
         m = Module()
         m.submodules.jtag = self.jtag
+        m.submodules.sram = self.sram
+
         count = Signal(5)
         m.d.sync += count.eq(5)
         print ("resources", platform.resources.items())
@@ -382,6 +405,11 @@ class ASICPlatform(TemplatedPlatform):
         m.d.comb += padpin.oe.eq(padport_oe)
         return m
 
+    def toolchain_prepare(self, fragment, name, **kwargs):
+        """override toolchain_prepare in order to grab the fragment
+        """
+        self.fragment = fragment
+        return super().toolchain_prepare(fragment, name, **kwargs)
 
 """
 and to create a Platform instance with that list, and build
@@ -393,8 +421,54 @@ something random
 """
 pinset = dummy_pinset()
 top = Blinker(pinset)
+
+# XXX these modules are all being added *AFTER* the build process links
+# everything together.  the expectation that this would work is... unrealistic.
+# ordering, clearly, is important.
+
+# dut = JTAG(test_pinset(), wb_data_wid=64, domain="sync")
+top.jtag.stop = False
+# rather than the client access the JTAG bus directly
+# create an alternative that the client sets
+class Dummy: pass
+cdut = Dummy()
+cdut.cbus = JTAGInterface()
+
+# set up client-server on port 44843-something
+top.jtag.s = JTAGServer()
+cdut.c = JTAGClient()
+top.jtag.s.get_connection()
+#else:
+#    print ("running server only as requested, use openocd remote to test")
+#    sys.stdout.flush()
+#    top.jtag.s.get_connection(None) # block waiting for connection
+
+# take copy of ir_width and scan_len
+cdut._ir_width = top.jtag._ir_width
+cdut.scan_len = top.jtag.scan_len
+
 print(pinset)
 resources = create_resources(pinset)
 p = ASICPlatform (resources, top.jtag)
 p.build(top)
-
+# this is what needs to gets treated as "top", after "main module" top
+# is augmented with IO pads with JTAG tacked on.  the expectation that
+# the get_input() etc functions will be called magically by some other
+# function is unrealistic.
+top_fragment = p.fragment
+
+# XXX simulating top (the module that does not itself contain IO pads
+# because that's covered by build) cannot possibly be expected to work
+# particularly when modules have been added *after* the platform build()
+# function has been called.
+
+sim = Simulator(top_fragment)
+sim.add_clock(1e-6, domain="sync")      # standard clock
+
+sim.add_sync_process(wrap(jtag_srv(top))) #? jtag server
+#if len(sys.argv) != 2 or sys.argv[1] != 'server':
+sim.add_sync_process(wrap(jtag_sim(cdut, top.jtag))) # actual jtag tester
+sim.add_sync_process(wrap(dmi_sim(top.jtag)))  # handles (pretends to be) DMI
+
+with sim.write_vcd("dmi2jtag_test_srv.vcd"):
+    sim.run()