#!/usr/bin/env python3
from nmigen.build.dsl import Resource, Subsignal, Pins
from nmigen.build.plat import TemplatedPlatform
-from nmigen.build.res import ResourceManager
+from nmigen.build.res import ResourceManager, ResourceError
from nmigen import Elaboratable, Signal, Module, Instance
from collections import OrderedDict
-from jtag import JTAG
+from jtag import JTAG, resiotypes
from copy import deepcopy
# Was thinking of using these functions, but skipped for simplicity for now
def dummy_pinset():
# sigh this needs to come from pinmux.
gpios = []
- for i in range(16):
+ for i in range(4):
gpios.append("%d*" % i)
return {'uart': ['tx+', 'rx-'],
'gpio': gpios,
# ridiculously-simple top-level module. doesn't even have a sync domain
-# and can't have one until a clock has been established by DummyPlatform.
+# and can't have one until a clock has been established by ASICPlatform.
class Blinker(Elaboratable):
def __init__(self, pinset):
- self.jtag = JTAG(pinset, "sync")
+ self.jtag = JTAG({}, "sync")
def elaborate(self, platform):
m = Module()
count = Signal(5)
m.d.sync += count.eq(5)
print ("resources", platform.resources.items())
- gpio = platform.core['gpio']
+ gpio = platform.request('gpio')
print (gpio, gpio.layout, gpio.fields)
# get the GPIO bank, mess about with some of the pins
m.d.comb += gpio.gpio0.o.eq(1)
m.d.comb += gpio.gpio1.oe.eq(count[4])
m.d.sync += count[0].eq(gpio.gpio1.i)
# get the UART resource, mess with the output tx
- uart = platform.core['uart']
+ uart = platform.request('uart')
print (uart, uart.fields)
m.d.comb += uart.tx.eq(1)
return m
# sigh, have to create a dummy platform for now.
# TODO: investigate how the heck to get it to output ilang. or verilog.
# or, anything, really. but at least it doesn't barf
-class DummyPlatform(TemplatedPlatform):
+class ASICPlatform(TemplatedPlatform):
connectors = []
resources = OrderedDict()
required_tools = []
toolchain = None
default_clk = "clk" # should be picked up / overridden by platform sys.clk
default_rst = "rst" # should be picked up / overridden by platform sys.rst
- def __init__(self, pinset):
+
+ def __init__(self, resources, jtag):
+ self.pad_mgr = ResourceManager([], [])
+ self.jtag = jtag
super().__init__()
# create set of pin resources based on the pinset, this is for the core
- resources = create_resources(pinset)
self.add_resources(resources)
- # make a *second* - identical - set of pin resources for the IO ring
- padres = deepcopy(resources)
- self.pad_mgr = ResourceManager(padres, [])
- # allocate all resources, right now, so that a lookup can be created
- # between core IO names and pads
- self.core = {}
- self.pads = {}
- # request every single peripheral in the pinset.
- for periph, pins in pinset.items():
- self.core[periph] = self.request(periph)
- self.pads[periph] = self.pad_mgr.request(periph)
- # now create a lookup between the pad and the core, so that
- # JTAG boundary scan can be inserted in between
+ # record resource lookup between core IO names and pads
self.padlookup = {}
- core = list(self.iter_single_ended_pins())
- pads = list(self.pad_mgr.iter_single_ended_pins())
+
+ def request(self, name, number=0, *, dir=None, xdr=None):
+ """request a Resource (e.g. name="uart", number=0) which will
+ return a data structure containing Records of all the pins.
+
+ this override will also - automatically - create a JTAG Boundary Scan
+ connection *without* any change to the actual Platform.request() API
+ """
+ # okaaaay, bit of shenanigens going on: the important data structure
+ # here is Resourcemanager._ports. requests add to _ports, which is
+ # what needs redirecting. therefore what has to happen is to
+ # capture the number of ports *before* the request. sigh.
+ start_ports = len(self._ports)
+ value = super().request(name, number, dir=dir, xdr=xdr)
+ end_ports = len(self._ports)
+
+ # now make a corresponding (duplicate) request to the pad manager
+ # BUT, if it doesn't exist, don't sweat it: all it means is, the
+ # application did not request Boundary Scan for that resource.
+ pad_start_ports = len(self.pad_mgr._ports)
+ try:
+ pvalue = self.pad_mgr.request(name, number, dir=dir, xdr=xdr)
+ except AssertionError:
+ return value
+ pad_end_ports = len(self.pad_mgr._ports)
+
+ # ok now we have the lengths: now create a lookup between the pad
+ # and the core, so that JTAG boundary scan can be inserted in between
+ core = self._ports[start_ports:end_ports]
+ pads = self.pad_mgr._ports[pad_start_ports:pad_end_ports]
+ # oops if not the same numbers added. it's a duplicate. shouldn't happen
+ assert len(core) == len(pads), "argh, resource manager error"
print ("core", core)
print ("pads", pads)
+
+ # pad/core each return a list of tuples of (res, pin, port, attrs)
for pad, core in zip(pads, core):
- print ("iter", pad)
- self.padlookup[pad[0].name] = core
+ # create a lookup on pin name to get at the hidden pad instance
+ # this pin name will be handed to get_input, get_output etc.
+ # and without the padlookup you can't find the (duplicate) pad.
+ # note that self.padlookup and self.jtag.ios use the *exact* same
+ # pin.name per pin
+ pin = pad[1]
+ corepin = core[1]
+ if pin is None: continue # skip when pin is None
+ assert corepin is not None # if pad was None, core should be too
+ print ("iter", pad, pin.name)
+ assert pin.name not in self.padlookup # no overwrites allowed!
+ assert pin.name == corepin.name # has to be the same!
+ self.padlookup[pin.name] = pad # store pad by pin name
+
+ # now add the IO Shift Register. first identify the type
+ # then request a JTAG IOConn. we can't wire it up (yet) because
+ # we don't have a Module() instance. doh. that comes in get_input
+ # and get_output etc. etc.
+ iotype = resiotypes[pin.dir] # look up the C4M-JTAG IOType
+ io = self.jtag.add_io(iotype=iotype, name=pin.name) # create IOConn
+ self.jtag.ios[pin.name] = io # store IOConn Record by pin name
+
+ # finally return the value just like ResourceManager.request()
+ return value
+
+ def add_resources(self, resources, no_boundary_scan=False):
+ super().add_resources(resources)
+ if no_boundary_scan:
+ return
+ # make a *second* - identical - set of pin resources for the IO ring
+ padres = deepcopy(resources)
+ self.pad_mgr.add_resources(padres)
# XXX these aren't strictly necessary right now but the next
# phase is to add JTAG Boundary Scan so it maaay be worth adding?
def get_input(self, pin, port, attrs, invert):
self._check_feature("single-ended input", pin, attrs,
valid_xdrs=(0,), valid_attrs=None)
-
+ # Create a module first
+ m=Module()
print (" get_input", pin, "port", port, port.layout)
if pin.name not in ['clk_0', 'rst_0']: # sigh
- pad = self.padlookup[pin.name]
- print (" pad", pad)
- m = Module()
- m.d.comb += pin.i.eq(self._invert_if(invert, port))
+ (res, pin, port, attrs) = self.padlookup[pin.name]
+ io = self.jtag.ios[pin.name]
+ print (" pad", res, pin, port, attrs)
+ print (" pin", pin.layout)
+ print (" jtag", io.core.layout, io.pad.layout)
+ # Layout basically contains the list of objects (and sizes)
+ # so a Layout of [('i', 1)] means, "this object has a Signal
+ # named i and it is of length 1". threfore:
+ # * pin has a pin.i of length 1
+ # * io.core has an io.core.i of length 1
+ # * io.pad has an io.pad.i of length 1
+ # Your Mission, Should You Choose To Accept It, is to
+ # work out which bleeding way round what the hell is
+ # connected to what.
+ m.d.comb += io.pad.i.eq(self._invert_if(invert, port))
+ m.d.comb += pin.i.eq(io.core.i)
+ else: # simple pass-through from port to pin
+ print("No JTAG chain in-between")
+ m.d.comb += pin.i.eq(self._invert_if(invert, port))
return m
def get_output(self, pin, port, attrs, invert):
p.build(Blinker())
"""
pinset = dummy_pinset()
+top = Blinker(pinset)
print(pinset)
-p = DummyPlatform (pinset)
-p.build(Blinker(pinset))
+resources = create_resources(pinset)
+p = ASICPlatform (resources, top.jtag)
+p.build(top)
projects / pinmux.git / blobdiff