add comments and GPIO pads with triplet of Pins i/o/oe

[pinmux.git] / src / spec / testing_stage1.py

diff --git a/src/spec/testing_stage1.py b/src/spec/testing_stage1.py
index 7de2ef23d971ef0ca80ba60c12b6c9d592ce08c4..72f50545005597d0d1f93726d86cd4dbcbea082c 100644 (file)
--- a/src/spec/testing_stage1.py
+++ b/src/spec/testing_stage1.py
@@ -1,7 +1,7 @@
 #!/usr/bin/env python3
 from nmigen.build.dsl import Resource, Subsignal, Pins
 from nmigen.build.plat import TemplatedPlatform
-from nmigen import Elaboratable, Signal, Module
+from nmigen import Elaboratable, Signal, Module, Instance
 from collections import OrderedDict
 
 # Was thinking of using these functions, but skipped for simplicity for now
@@ -52,13 +52,29 @@ def create_resources(pinset):
             ios = []
             for pin in pins:
                 pname = "gpio"+pin[:-1] # strip "*" on end
-                ios.append(Subsignal(pname, Pins(pname, assert_width=1)))
+                pads = []
+                # urrrr... tristsate and io assume a single pin which is
+                # of course exactly what we don't want in an ASIC: we want
+                # *all three* pins but the damn port is not outputted
+                # as a triplet, it's a single Record named "io". sigh.
+                # therefore the only way to get a triplet of i/o/oe
+                # is to *actually* create explicit triple pins
+                pads.append(Subsignal("i",
+                            Pins(pname+"_i", dir="i", assert_width=1)))
+                pads.append(Subsignal("o",
+                            Pins(pname+"_o", dir="o", assert_width=1)))
+                pads.append(Subsignal("oe",
+                            Pins(pname+"_oe", dir="oe", assert_width=1)))
+                ios.append(Resource.family(pname, 0, default_name=pname,
+                                                 ios=pads))
             resources.append(Resource.family(periph, 0, default_name="gpio",
                                              ios=ios))
 
     # add clock and reset
-    resources.append(Resource("clk", 0, Pins("sys_clk", dir="i")))
-    resources.append(Resource("rst", 0, Pins("sys_rst", dir="i")))
+    clk = Resource("clk", 0, Pins("sys_clk", dir="i"))
+    rst = Resource("rst", 0, Pins("sys_rst", dir="i"))
+    resources.append(clk)
+    resources.append(rst)
     return resources
 
 
@@ -91,6 +107,8 @@ class Blinker(Elaboratable):
         # get the GPIO bank, mess about with some of the pins
         m.d.comb += gpio.gpio0.o.eq(1)
         m.d.comb += gpio.gpio1.o.eq(gpio.gpio2.i)
+        m.d.comb += gpio.gpio1.oe.eq(count[4])
+        m.d.sync += count[0].eq(gpio.gpio1.i)
         # get the UART resource, mess with the output tx
         uart = platform.request("uart", 0)
         print (uart, uart.fields)
@@ -136,6 +154,7 @@ class DummyPlatform(TemplatedPlatform):
         super().__init__()
         self.add_resources(resources)
 
+
 """
 and to create a Platform instance with that list, and build
 something random