from nmigen.build.res import ResourceManager, ResourceError
from nmigen import Elaboratable, Signal, Module, Instance
from collections import OrderedDict
-from jtag import JTAG
+from jtag import JTAG, resiotypes
from copy import deepcopy
# Was thinking of using these functions, but skipped for simplicity for now
def dummy_pinset():
# sigh this needs to come from pinmux.
gpios = []
- for i in range(16):
+ for i in range(4):
gpios.append("%d*" % i)
return {'uart': ['tx+', 'rx-'],
'gpio': gpios,
ios = []
for pin in pins:
pname = "gpio"+pin[:-1] # strip "*" on end
- pads = []
# urrrr... tristsate and io assume a single pin which is
# of course exactly what we don't want in an ASIC: we want
# *all three* pins but the damn port is not outputted
# as a triplet, it's a single Record named "io". sigh.
# therefore the only way to get a triplet of i/o/oe
# is to *actually* create explicit triple pins
- pads.append(Subsignal("i",
- Pins(pname+"_i", dir="i", assert_width=1)))
- pads.append(Subsignal("o",
- Pins(pname+"_o", dir="o", assert_width=1)))
- pads.append(Subsignal("oe",
- Pins(pname+"_oe", dir="oe", assert_width=1)))
- ios.append(Resource.family(pname, 0, default_name=pname,
- ios=pads))
+ pad = Subsignal("io",
+ Pins("%s_i %s_o %s_oe" % (pname, pname, pname),
+ dir="io", assert_width=3))
+ ios.append(Resource(pname, 0, pad))
resources.append(Resource.family(periph, 0, default_name="gpio",
ios=ios))
# ridiculously-simple top-level module. doesn't even have a sync domain
-# and can't have one until a clock has been established by DummyPlatform.
+# and can't have one until a clock has been established by ASICPlatform.
class Blinker(Elaboratable):
def __init__(self, pinset):
- self.jtag = JTAG(pinset, "sync")
+ self.jtag = JTAG({}, "sync")
def elaborate(self, platform):
m = Module()
gpio = platform.request('gpio')
print (gpio, gpio.layout, gpio.fields)
# get the GPIO bank, mess about with some of the pins
- m.d.comb += gpio.gpio0.o.eq(1)
- m.d.comb += gpio.gpio1.o.eq(gpio.gpio2.i)
- m.d.comb += gpio.gpio1.oe.eq(count[4])
- m.d.sync += count[0].eq(gpio.gpio1.i)
+ m.d.comb += gpio.gpio0.io.o.eq(1)
+ m.d.comb += gpio.gpio1.io.o.eq(gpio.gpio2.io.i)
+ m.d.comb += gpio.gpio1.io.oe.eq(count[4])
+ m.d.sync += count[0].eq(gpio.gpio1.io.i)
# get the UART resource, mess with the output tx
uart = platform.request('uart')
print (uart, uart.fields)
# sigh, have to create a dummy platform for now.
# TODO: investigate how the heck to get it to output ilang. or verilog.
# or, anything, really. but at least it doesn't barf
-class DummyPlatform(TemplatedPlatform):
+class ASICPlatform(TemplatedPlatform):
connectors = []
resources = OrderedDict()
required_tools = []
toolchain = None
default_clk = "clk" # should be picked up / overridden by platform sys.clk
default_rst = "rst" # should be picked up / overridden by platform sys.rst
- def __init__(self, pinset):
+
+ def __init__(self, resources, jtag):
self.pad_mgr = ResourceManager([], [])
+ self.jtag = jtag
super().__init__()
# create set of pin resources based on the pinset, this is for the core
- resources = create_resources(pinset)
self.add_resources(resources)
# record resource lookup between core IO names and pads
self.padlookup = {}
def request(self, name, number=0, *, dir=None, xdr=None):
+ """request a Resource (e.g. name="uart", number=0) which will
+ return a data structure containing Records of all the pins.
+
+ this override will also - automatically - create a JTAG Boundary Scan
+ connection *without* any change to the actual Platform.request() API
+ """
# okaaaay, bit of shenanigens going on: the important data structure
# here is Resourcemanager._ports. requests add to _ports, which is
# what needs redirecting. therefore what has to happen is to
end_ports = len(self._ports)
# now make a corresponding (duplicate) request to the pad manager
- # BUT, if it doesn't exist, don't sweat it
+ # BUT, if it doesn't exist, don't sweat it: all it means is, the
+ # application did not request Boundary Scan for that resource.
pad_start_ports = len(self.pad_mgr._ports)
try:
pvalue = self.pad_mgr.request(name, number, dir=dir, xdr=xdr)
print ("core", core)
print ("pads", pads)
- # each of these returns a tuple (res, pin, port, attrs)
+ # pad/core each return a list of tuples of (res, pin, port, attrs)
for pad, core in zip(pads, core):
+ # create a lookup on pin name to get at the hidden pad instance
+ # this pin name will be handed to get_input, get_output etc.
+ # and without the padlookup you can't find the (duplicate) pad.
+ # note that self.padlookup and self.jtag.ios use the *exact* same
+ # pin.name per pin
pin = pad[1]
corepin = core[1]
if pin is None: continue # skip when pin is None
assert corepin is not None # if pad was None, core should be too
print ("iter", pad, pin.name)
+ print ("existing pads", self.padlookup.keys())
assert pin.name not in self.padlookup # no overwrites allowed!
- assert pin.name == corepin.name # has to be the same!
- self.padlookup[pin.name] = core
+ assert pin.name == corepin.name # has to be the same!
+ self.padlookup[pin.name] = pad # store pad by pin name
+
+ # now add the IO Shift Register. first identify the type
+ # then request a JTAG IOConn. we can't wire it up (yet) because
+ # we don't have a Module() instance. doh. that comes in get_input
+ # and get_output etc. etc.
+ iotype = resiotypes[pin.dir] # look up the C4M-JTAG IOType
+ io = self.jtag.add_io(iotype=iotype, name=pin.name) # create IOConn
+ self.jtag.ios[pin.name] = io # store IOConn Record by pin name
# finally return the value just like ResourceManager.request()
return value
self._check_feature("single-ended input", pin, attrs,
valid_xdrs=(0,), valid_attrs=None)
- print (" get_input", pin, "port", port, port.layout)
- if pin.name not in ['clk_0', 'rst_0']: # sigh
- pad = self.padlookup[pin.name]
- print (" pad", pad)
m = Module()
- m.d.comb += pin.i.eq(self._invert_if(invert, port))
+ print (" get_input", pin, "port", port, port.layout)
+ if pin.name in ['clk_0', 'rst_0']: # sigh
+ # simple pass-through from port to pin
+ print("No JTAG chain in-between")
+ m.d.comb += pin.i.eq(self._invert_if(invert, port))
+ return m
+ (res, pin, port, attrs) = self.padlookup[pin.name]
+ io = self.jtag.ios[pin.name]
+ print (" pad", res, pin, port, attrs)
+ print (" pin", pin.layout)
+ print (" jtag", io.core.layout, io.pad.layout)
+ m.d.comb += io.pad.i.eq(self._invert_if(invert, port))
+ m.d.comb += pin.i.eq(io.core.i)
return m
def get_output(self, pin, port, attrs, invert):
self._check_feature("single-ended output", pin, attrs,
valid_xdrs=(0,), valid_attrs=None)
- print (" get_output", pin, "port", port, port.layout)
m = Module()
- m.d.comb += port.eq(self._invert_if(invert, pin.o))
+ print (" get_output", pin, "port", port, port.layout)
+ if pin.name in ['clk_0', 'rst_0']: # sigh
+ # simple pass-through from pin to port
+ print("No JTAG chain in-between")
+ m.d.comb += port.eq(self._invert_if(invert, pin.o))
+ return m
+ (res, pin, port, attrs) = self.padlookup[pin.name]
+ io = self.jtag.ios[pin.name]
+ print (" pad", res, pin, port, attrs)
+ print (" pin", pin.layout)
+ print (" jtag", io.core.layout, io.pad.layout)
+ m.d.comb += port.eq(self._invert_if(invert, io.pad.o))
+ m.d.comb += pin.o.eq(io.core.o)
return m
def get_tristate(self, pin, port, attrs, invert):
self._check_feature("single-ended tristate", pin, attrs,
valid_xdrs=(0,), valid_attrs=None)
+ print (" get_tristate", pin, "port", port, port.layout)
m = Module()
- m.submodules += Instance("$tribuf",
- p_WIDTH=pin.width,
- i_EN=pin.oe,
- i_A=self._invert_if(invert, pin.o),
- o_Y=port,
- )
+ if pin.name in ['clk_0', 'rst_0']: # sigh
+ print("No JTAG chain in-between")
+ # Can port's i/o/oe be accessed like this?
+ m.d.comb += port.o.eq(pin.o)
+ m.d.comb += port.oe.eq(pin.oe)
+ m.d.comb += pin.i.eq(port.i)
+ return m
+ (res, pin, port, attrs) = self.padlookup[pin.name]
+ io = self.jtag.ios[pin.name]
+ print (" pad", res, pin, port, attrs)
+ print (" pin", pin.layout)
+ print (" jtag", io.core.layout, io.pad.layout)
+ m.d.comb += io.core.o.eq(pin.o)
+ m.d.comb += io.core.oe.eq(pin.oe)
+ m.d.comb += pin.i.eq(io.core.i)
+ m.d.comb += io.pad.i.eq(port.i)
+ m.d.comb += port.o.eq(io.pad.o)
+ m.d.comb += port.oe.eq(io.pad.oe)
return m
def get_input_output(self, pin, port, attrs, invert):
self._check_feature("single-ended input/output", pin, attrs,
valid_xdrs=(0,), valid_attrs=None)
+
print (" get_input_output", pin, "port", port, port.layout)
- m = Module()
+ m = Module()
+ if pin.name in ['clk_0', 'rst_0']: # sigh
+ print("No JTAG chain in-between")
+ m.submodules += Instance("$tribuf",
+ p_WIDTH=pin.width,
+ i_EN=pin.oe,
+ i_A=self._invert_if(invert, pin.o),
+ o_Y=port,
+ )
+ m.d.comb += pin.i.eq(self._invert_if(invert, port))
+ return m
+ (res, pin, port, attrs) = self.padlookup[pin.name]
+ io = self.jtag.ios[pin.name]
+ print (" pad", res, pin, port, attrs)
+ print (" pin", pin.layout)
+ print (" jtag", io.core.layout, io.pad.layout)
m.submodules += Instance("$tribuf",
p_WIDTH=pin.width,
- i_EN=pin.oe,
- i_A=self._invert_if(invert, pin.o),
+ i_EN=io.pad.oe,
+ i_A=self._invert_if(invert, io.pad.o),
o_Y=port,
)
- m.d.comb += pin.i.eq(self._invert_if(invert, port))
+ m.d.comb += io.pad.i.eq(self._invert_if(invert, port))
+ m.d.comb += pin.i.eq(io.core.i)
+ m.d.comb += io.core.o.eq(pin.o)
+ m.d.comb += io.core.oe.eq(pin.oe)
return m
p.build(Blinker())
"""
pinset = dummy_pinset()
+top = Blinker(pinset)
print(pinset)
-p = DummyPlatform (pinset)
-p.build(Blinker(pinset))
+resources = create_resources(pinset)
+p = ASICPlatform (resources, top.jtag)
+p.build(top)
projects / pinmux.git / blobdiff