ios = []
for pin in pins:
pname = "gpio"+pin[:-1] # strip "*" on end
- pads = []
# urrrr... tristsate and io assume a single pin which is
# of course exactly what we don't want in an ASIC: we want
# *all three* pins but the damn port is not outputted
# as a triplet, it's a single Record named "io". sigh.
# therefore the only way to get a triplet of i/o/oe
# is to *actually* create explicit triple pins
- pads.append(Subsignal("i",
- Pins(pname+"_i", dir="i", assert_width=1)))
- pads.append(Subsignal("o",
- Pins(pname+"_o", dir="o", assert_width=1)))
- pads.append(Subsignal("oe",
- Pins(pname+"_oe", dir="oe", assert_width=1)))
- ios.append(Resource.family(pname, 0, default_name=pname,
- ios=pads))
+ pad = Subsignal("io",
+ Pins("%s_i %s_o %s_oe" % (pname, pname, pname),
+ dir="io", assert_width=3))
+ ios.append(Resource(pname, 0, pad))
resources.append(Resource.family(periph, 0, default_name="gpio",
ios=ios))
gpio = platform.request('gpio')
print (gpio, gpio.layout, gpio.fields)
# get the GPIO bank, mess about with some of the pins
- m.d.comb += gpio.gpio0.o.eq(1)
- m.d.comb += gpio.gpio1.o.eq(gpio.gpio2.i)
- m.d.comb += gpio.gpio1.oe.eq(count[4])
- m.d.sync += count[0].eq(gpio.gpio1.i)
+ m.d.comb += gpio.gpio0.io.o.eq(1)
+ m.d.comb += gpio.gpio1.io.o.eq(gpio.gpio2.io.i)
+ m.d.comb += gpio.gpio1.io.oe.eq(count[4])
+ m.d.sync += count[0].eq(gpio.gpio1.io.i)
# get the UART resource, mess with the output tx
uart = platform.request('uart')
print (uart, uart.fields)
- m.d.comb += uart.tx.eq(1)
+ intermediary = Signal()
+ m.d.comb += uart.tx.eq(intermediary)
+ m.d.comb += intermediary.eq(uart.rx)
return m
if pin is None: continue # skip when pin is None
assert corepin is not None # if pad was None, core should be too
print ("iter", pad, pin.name)
+ print ("existing pads", self.padlookup.keys())
assert pin.name not in self.padlookup # no overwrites allowed!
assert pin.name == corepin.name # has to be the same!
self.padlookup[pin.name] = pad # store pad by pin name
padres = deepcopy(resources)
self.pad_mgr.add_resources(padres)
+ #def iter_ports(self):
+ # yield from super().iter_ports()
+ # for io in self.jtag.ios.values():
+ # print ("iter ports", io.layout, io)
+ # for field in io.core.fields:
+ # yield getattr(io.core, field)
+ # for field in io.pad.fields:
+ # yield getattr(io.pad, field)
+
# XXX these aren't strictly necessary right now but the next
# phase is to add JTAG Boundary Scan so it maaay be worth adding?
# at least for the print statements
print("No JTAG chain in-between")
m.d.comb += pin.i.eq(self._invert_if(invert, port))
return m
- (res, pin, port, attrs) = self.padlookup[pin.name]
+ (padres, padpin, padport, padattrs) = self.padlookup[pin.name]
io = self.jtag.ios[pin.name]
- print (" pad", res, pin, port, attrs)
- print (" pin", pin.layout)
+ print (" pad", padres, padpin, padport, attrs)
+ print (" padpin", padpin.layout)
print (" jtag", io.core.layout, io.pad.layout)
- m.d.comb += io.pad.i.eq(self._invert_if(invert, port))
- m.d.comb += pin.i.eq(io.core.i)
+ m.d.comb += pin.i.eq(self._invert_if(invert, port))
+ m.d.comb += padpin.i.eq(padport)
+ m.d.comb += padport.io.eq(io.core.i)
+ m.d.comb += io.pad.i.eq(pin.i)
return m
def get_output(self, pin, port, attrs, invert):
print("No JTAG chain in-between")
m.d.comb += port.eq(self._invert_if(invert, pin.o))
return m
- (res, pin, port, attrs) = self.padlookup[pin.name]
+ (padres, padpin, padport, padattrs) = self.padlookup[pin.name]
io = self.jtag.ios[pin.name]
- print (" pad", res, pin, port, attrs)
- print (" pin", pin.layout)
+ print (" pad", padres, padpin, padport, padattrs)
+ print (" pin", padpin.layout)
print (" jtag", io.core.layout, io.pad.layout)
- m.d.comb += port.eq(self._invert_if(invert, io.pad.o))
- m.d.comb += pin.o.eq(io.core.o)
+ m.d.comb += port.eq(self._invert_if(invert, pin.o))
+ m.d.comb += padport.io.eq(self._invert_if(invert, padpin.o))
+ m.d.comb += io.core.o.eq(port.io)
+ m.d.comb += padpin.o.eq(io.pad.o)
return m
def get_tristate(self, pin, port, attrs, invert):
m = Module()
if pin.name in ['clk_0', 'rst_0']: # sigh
print("No JTAG chain in-between")
- # Can port's i/o/oe be accessed like this?
- m.d.comb += port.o.eq(pin.o)
- m.d.comb += port.oe.eq(pin.oe)
- m.d.comb += pin.i.eq(port.i)
+ m.submodules += Instance("$tribuf",
+ p_WIDTH=pin.width,
+ i_EN=pin.oe,
+ i_A=self._invert_if(invert, pin.o),
+ o_Y=port,
+ )
return m
(res, pin, port, attrs) = self.padlookup[pin.name]
io = self.jtag.ios[pin.name]
print (" pad", res, pin, port, attrs)
print (" pin", pin.layout)
print (" jtag", io.core.layout, io.pad.layout)
+ #m.submodules += Instance("$tribuf",
+ # p_WIDTH=pin.width,
+ # i_EN=io.pad.oe,
+ # i_A=self._invert_if(invert, io.pad.o),
+ # o_Y=port,
+ #)
m.d.comb += io.core.o.eq(pin.o)
m.d.comb += io.core.oe.eq(pin.oe)
m.d.comb += pin.i.eq(io.core.i)
io = self.jtag.ios[pin.name]
print (" pad", res, pin, port, attrs)
print (" pin", pin.layout)
+ print (" port layout", port.layout)
print (" jtag", io.core.layout, io.pad.layout)
- m.submodules += Instance("$tribuf",
- p_WIDTH=pin.width,
- i_EN=io.pad.oe,
- i_A=self._invert_if(invert, io.pad.o),
- o_Y=port,
- )
- m.d.comb += io.pad.i.eq(self._invert_if(invert, port))
+ #m.submodules += Instance("$tribuf",
+ # p_WIDTH=pin.width,
+ # i_EN=io.pad.oe,
+ # i_A=self._invert_if(invert, io.pad.o),
+ # o_Y=port,
+ #)
+ port_i = port.io[0]
+ port_o = port.io[1]
+ port_oe = port.io[2]
+ m.d.comb += io.pad.i.eq(self._invert_if(invert, port_i))
+ m.d.comb += port_o.eq(self._invert_if(invert, io.pad.o))
+ m.d.comb += port_oe.eq(io.pad.o)
m.d.comb += pin.i.eq(io.core.i)
m.d.comb += io.core.o.eq(pin.o)
m.d.comb += io.core.oe.eq(pin.oe)
projects / pinmux.git / blobdiff