import sys
# extra dependencies for jtag testing (?)
-from soc.bus.sram import SRAM
+#from soc.bus.sram import SRAM
-from nmigen import Memory
-from nmigen.sim import Simulator, Delay, Settle, Tick
+#from nmigen import Memory
+from nmigen.sim import Simulator, Delay, Settle, Tick, Passive
from nmutil.util import wrap
-from soc.debug.jtagutils import (jtag_read_write_reg,
- jtag_srv, jtag_set_reset,
- jtag_set_ir, jtag_set_get_dr)
+#from soc.debug.jtagutils import (jtag_read_write_reg,
+# jtag_srv, jtag_set_reset,
+# jtag_set_ir, jtag_set_get_dr)
from c4m.nmigen.jtag.tap import TAP, IOType
from c4m.nmigen.jtag.bus import Interface as JTAGInterface
-from soc.debug.dmi import DMIInterface, DBGCore
-from soc.debug.test.dmi_sim import dmi_sim
-from soc.debug.test.jtagremote import JTAGServer, JTAGClient
+#from soc.debug.dmi import DMIInterface, DBGCore
+#from soc.debug.test.dmi_sim import dmi_sim
+#from soc.debug.test.jtagremote import JTAGServer, JTAGClient
from nmigen.build.res import ResourceError
# Was thinking of using these functions, but skipped for simplicity for now
class Blinker(Elaboratable):
def __init__(self, pinset, resources):
self.jtag = JTAG({}, "sync", resources=resources)
- memory = Memory(width=32, depth=16)
- self.sram = SRAM(memory=memory, bus=self.jtag.wb)
+ #memory = Memory(width=32, depth=16)
+ #self.sram = SRAM(memory=memory, bus=self.jtag.wb)
def elaborate(self, platform):
jtag_resources = self.jtag.pad_mgr.resources
m = Module()
m.submodules.jtag = self.jtag
- m.submodules.sram = self.sram
+ #m.submodules.sram = self.sram
count = Signal(5)
m.d.sync += count.eq(count+1)
# get the UART resource, mess with the output tx
uart = self.jtag.request('uart')
print (uart, uart.fields)
- intermediary = Signal()
- m.d.comb += uart.tx.eq(intermediary)
- m.d.comb += intermediary.eq(uart.rx)
+ self.intermediary = Signal()
+ m.d.comb += uart.tx.eq(self.intermediary)
+ m.d.comb += self.intermediary.eq(uart.rx)
+
+ # to even be able to get at objects, you first have to make them
+ # available - i.e. not as local variables
+ self.gpio = gpio
+ self.uart = uart
return self.jtag.boundary_elaborate(m, platform)
with open("test_jtag_blinker.il", "w") as f:
f.write(vl)
-if True:
+if False:
# XXX these modules are all being added *AFTER* the build process links
# everything together. the expectation that this would work is...
# unrealistic. ordering, clearly, is important.
# particularly when modules have been added *after* the platform build()
# function has been called.
+def test_case0():
+ print("Starting sanity test case!")
+ print("printing out list of stuff in top")
+ print(dir(top))
+ # ok top now has a variable named "gpio", let's enumerate that too
+ print("printing out list of stuff in top.gpio and its type")
+ print(top.gpio.__class__.__name__, dir(top.gpio))
+ # ok, it's a nmigen Record, therefore it has a layout. let's print
+ # that too
+ print("top.gpio is a Record therefore has fields and a layout")
+ print(" layout:", top.gpio.layout)
+ print(" fields:", top.gpio.fields)
+ print("Fun never ends...")
+ print(" layout, gpio2:", top.gpio.layout['gpio2'])
+ print(" fields, gpio2:", top.gpio.fields['gpio2'])
+ print(top.jtag.__class__.__name__, dir(top.jtag))
+
+ # etc etc. you get the general idea
+ delayVal = 0.2e-6
+ yield top.uart.rx.eq(0)
+ yield Delay(delayVal)
+ yield Settle()
+ yield top.gpio.gpio2.o.eq(0)
+ yield top.gpio.gpio3.o.eq(1)
+ yield Delay(delayVal)
+ yield Settle()
+ yield top.gpio.gpio2.oe.eq(1)
+ yield top.gpio.gpio3.oe.eq(1)
+ #yield top.jtag.gpio.gpio2.i.eq(1)
+ yield Delay(delayVal)
+ yield Settle()
+ for _ in range(20):
+ # get a value first (as an integer). you were trying to set
+ # it to the actual Signal
+ gpio_o2 = yield top.gpio.gpio2.o
+ # then set it
+ yield top.gpio.gpio2.o.eq(~gpio_o2)
+
+ # ditto: here you are trying to set to an AST expression
+ # which is inadviseable (likely to fail)
+ yield top.gpio.gpio3.o.eq(~top.gpio.gpio3.o)
+ yield Delay(delayVal)
+ yield Settle()
+ # again you are trying to set something equal to the Signal
+ # rather than to a value. this is attempting to change the
+ # actual HDL which is completely inappropriate
+ yield top.uart.rx.eq(~top.intermediary)
+ yield Delay(delayVal)
+ yield Settle()
+
+ yield top.gpio.gpio2.oe.eq(0)
+ yield top.gpio.gpio3.oe.eq(0)
+ #yield top.jtag.gpio.gpio2.i.eq(0)
+ yield Delay(delayVal)
+ yield Settle()
+
+# Code borrowed from cesar, runs, but shouldn't actually work because of
+# self. statements and non-existent signal names.
+def test_case1():
+ print("Example test case")
+ yield Passive()
+ while True:
+ # Settle() is needed to give a quick response to
+ # the zero delay case
+ yield Settle()
+ # wait for rel_o to become active
+ while not (yield self.rel_o):
+ yield
+ yield Settle()
+ # read the transaction parameters
+ assert self.expecting, "an unexpected result was produced"
+ delay = (yield self.delay)
+ expected = (yield self.expected)
+ # wait for `delay` cycles
+ for _ in range(delay):
+ yield
+ # activate go_i for one cycle
+ yield self.go_i.eq(1)
+ yield self.count.eq(self.count + 1)
+ yield
+ # check received data against the expected value
+ result = (yield self.port)
+ assert result == expected,\
+ f"expected {expected}, received {result}"
+ yield self.go_i.eq(0)
+ yield self.port.eq(0)
+
sim = Simulator(top)
sim.add_clock(1e-6, domain="sync") # standard clock
-sim.add_sync_process(wrap(jtag_srv(top))) #? jtag server
+#sim.add_sync_process(wrap(jtag_srv(top))) #? jtag server
#if len(sys.argv) != 2 or sys.argv[1] != 'server':
-sim.add_sync_process(wrap(jtag_sim(cdut, top.jtag))) # actual jtag tester
-sim.add_sync_process(wrap(dmi_sim(top.jtag))) # handles (pretends to be) DMI
+#sim.add_sync_process(wrap(jtag_sim(cdut, top.jtag))) # actual jtag tester
+#sim.add_sync_process(wrap(dmi_sim(top.jtag))) # handles (pretends to be) DMI
+
+#sim.add_sync_process(wrap(test_case1()))
+sim.add_sync_process(wrap(test_case0()))
-with sim.write_vcd("dmi2jtag_test_srv.vcd"):
+with sim.write_vcd("blinker_test.vcd"):
sim.run()
projects / pinmux.git / blobdiff