testing comments

[pinmux.git] / src / spec / testing_stage1.py

diff --git a/src/spec/testing_stage1.py b/src/spec/testing_stage1.py
index c0fbc8eb014ead96a710440f87ad8b3806834bd1..aa888079645612c726fda6912f5b2d2a71411e87 100644 (file)
--- a/src/spec/testing_stage1.py
+++ b/src/spec/testing_stage1.py
@@ -168,13 +168,14 @@ class Blinker(Elaboratable):
         # get the UART resource, mess with the output tx
         uart = self.jtag.request('uart')
         print (uart, uart.fields)
-        intermediary = Signal()
-        m.d.comb += uart.tx.eq(intermediary)
-        m.d.comb += intermediary.eq(uart.rx)
+        self.intermediary = Signal()
+        m.d.comb += uart.tx.eq(self.intermediary)
+        m.d.comb += self.intermediary.eq(uart.rx)
 
         # to even be able to get at objects, you first have to make them
         # available - i.e. not as local variables
         self.gpio = gpio
+        self.uart = uart
 
         return self.jtag.boundary_elaborate(m, platform)
 
@@ -387,11 +388,49 @@ def test_case0():
     print("top.gpio is a Record therefore has fields and a layout")
     print("    layout:", top.gpio.layout)
     print("    fields:", top.gpio.fields)
+    print("Fun never ends...")
+    print("    layout, gpio2:", top.gpio.layout['gpio2'])
+    print("    fields, gpio2:", top.gpio.fields['gpio2'])
+    print(top.jtag.__class__.__name__, dir(top.jtag))
+
     # etc etc. you get the general idea
-    yield top.gpio_0__gpio0__o__o.eq(0)
-    yield top.gpio_0__gpio0__o__core__o.eq(0)
-    yield top.gpio_0__gpio1__o.eq(0)
-    yield 
+    delayVal = 0.2e-6
+    yield top.uart.rx.eq(0)
+    yield Delay(delayVal)
+    yield Settle()
+    yield top.gpio.gpio2.o.eq(0)
+    yield top.gpio.gpio3.o.eq(1)
+    yield Delay(delayVal)
+    yield Settle()
+    yield top.gpio.gpio2.oe.eq(1)
+    yield top.gpio.gpio3.oe.eq(1)
+    #yield top.jtag.gpio.gpio2.i.eq(1)
+    yield Delay(delayVal)
+    yield Settle()
+    for _ in range(20):
+        # get a value first (as an integer).  you were trying to set
+        # it to the actual Signal
+        gpio_o2 = yield top.gpio.gpio2.o
+        # then set it
+        yield top.gpio.gpio2.o.eq(~gpio_o2)
+
+        # ditto: here you are trying to set to an AST expression
+        # which is inadviseable (likely to fail)
+        yield top.gpio.gpio3.o.eq(~top.gpio.gpio3.o)
+        yield Delay(delayVal)
+        yield Settle()
+        # again you are trying to set something equal to the Signal
+        # rather than to a value.  this is attempting to change the
+        # actual HDL which is completely inappropriate
+        yield top.uart.rx.eq(~top.intermediary)
+        yield Delay(delayVal)
+        yield Settle()
+    
+    yield top.gpio.gpio2.oe.eq(0)
+    yield top.gpio.gpio3.oe.eq(0)
+    #yield top.jtag.gpio.gpio2.i.eq(0)
+    yield Delay(delayVal)
+    yield Settle()
 
 # Code borrowed from cesar, runs, but shouldn't actually work because of
 # self. statements and non-existent signal names.
@@ -432,7 +471,7 @@ sim.add_clock(1e-6, domain="sync")      # standard clock
 #sim.add_sync_process(wrap(jtag_sim(cdut, top.jtag))) # actual jtag tester
 #sim.add_sync_process(wrap(dmi_sim(top.jtag)))  # handles (pretends to be) DMI
 
-sim.add_sync_process(wrap(test_case1()))
+#sim.add_sync_process(wrap(test_case1()))
 sim.add_sync_process(wrap(test_case0()))
 
 with sim.write_vcd("blinker_test.vcd"):